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Commercial CMOS Process for Quantum Computing: Quantum Dots and Charge Sensing in a 22 nm Fully Depleted Silicon-on-Insulator Process

T0 review · 3 major / 6 minor · reviewed 2026-08-11 · deepseek-v4-flash

Pith's one-line read Commercial 22 nm CMOS hosts quantum dots with an on-chip charge sensor

desk verdict A plausible engineering demonstration of quantum dots plus SEB sensing in unmodified 22 nm FDSOI, but the multi-dot sensing leg is self-admittedly unmodeled and the 'first time' claim needs a benchmark. read the letter →

arxiv 2412.08422 v2 pith:6QZU4ISD submitted 2024-12-11 cond-mat.mes-hall quant-ph

classification cond-mat.mes-hallquant-ph PACS 73.63.Kv85.35.Gv03.67.Lx
keywords quantumdotssiliconspinqubitsFDSOICMOSsingle-electronboxchargesensingradio-frequencyreflectometrydotarraycryogenicelectronics
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reports that a quantum dot array can be operated inside a transistor-like structure made with an unmodified commercial 22 nm fully depleted silicon-on-insulator CMOS process. By biasing a combination of five electrostatic gates and a back gate, the authors form one or two quantum dots in the channel and control the tunnel barrier between them. They also reconfigure the same array into a single-electron box sensor at the array's edge and use it to detect charge transitions of neighboring single and double dots. If correct, this shows that the building blocks of a scalable spin-qubit processor, quantum dots plus integrated charge readout, can be produced in a standard chip foundry rather than in bespoke laboratory fabrication.

What carries the argument

The working object is a five-gate quantum dot array in a 22 nm FDSOI transistor: raised source and drain, gates QA0, QT0, QT1, QT2, QA1, and a back gate beneath the buried oxide. Dots are not controlled by dedicated plunger gates; instead, the back-gate voltage and the barrier-gate voltages together define the confinement and detune the dot energy levels. The inter-dot coupling is tuned by the central barrier gate QT1. The charge sensor is a single-lead single-electron box formed at the array edge, read out by rf reflectometry through a 75.5 MHz tank circuit; its quantum capacitance response reveals the charge transitions of adjacent dots.

What would settle it

Run the same device at base temperature and extract charging energies and tunnel couplings from Coulomb diamond sizes, bias-triangle dimensions, and SEB phase shifts. If these disagree with the assigned dot geometry, or if the claimed double-dot pattern can be reproduced by a single large dot with charge traps, the central interpretation collapses; a minimal check is whether SEB response jumps land exactly on the transport-defined triple points.

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Extended reading notes

Core claim

The central claim is that a commercial 22 nm FD-SOI process can simultaneously support electrostatically defined quantum dots and integrated charge sensing. In transport mode, two dots form between the barrier gate pairs QT0/QT1 and QT1/QT2; increasing the central barrier gate voltage VQT1 first separates the bias-triangle pairs at the triple points and eventually merges the two dots into one, demonstrating inter-dot coupling control. The same device is then biased as a single-electron box (SEB) adjacent to the array, and its rf-reflectometry response shows discrete jumps and shifted charge transitions as electrons load into one or two neighboring quantum dots. The authors present this as the first demonstration in a commercial CMOS process of controlling a multi-dot array and sensing its charge state with a SEB.

Load-bearing premise

The load-bearing premise is that the observed stability patterns and reflectometry responses are correctly read as electrostatically defined quantum dots and single-electron transitions; the identification rests on visual matching to standard diagrams, and for the SEB double-dot case the authors state that 'further analysis is needed to understand each transition in detail.'

Editorial extensions

If this is right

  • Quantum dot qubit hardware could be made in standard 22 nm FDSOI photolithography without changing the foundry process.
  • One device can be switched between transport operation, where bias triangles form, and sensing operation, where the SEB reads out the dots.
  • A single SEB at the array edge is sensitive enough to see charge transitions of both a single dot and a coupled double dot.
  • Barrier-gate and back-gate voltages together give enough control to detune dot levels and tune the inter-dot tunnel coupling, reducing the need for dedicated plunger gates.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A quantitative fit of charging energies and tunnel couplings from these diagrams would tell whether the array also supports more than two dots; the gate layout does not obviously limit the count.
  • The phase-sensitive reflectometry response to the double dot hints that quantum-capacitance readout could be used for spin-to-charge conversion, such as Pauli spin blockade, in this same process.
  • A natural cross-check is to compare the gate-voltage positions of SEB response jumps with the transport triple points while sweeping VQT1; a mismatch would show where the two interpretations diverge.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper reports electrical characterization of a five-gate quantum dot array fabricated in an unmodified GlobalFoundries 22FDX fully depleted silicon-on-insulator process. Transport measurements at 700 mK and 70 mK are used to claim formation of a double quantum dot, control of the inter-dot tunnel barrier via the central gate voltage VQT1, and observation of bias triangle pairs whose orientation and size depend on VDS. Reflectometry measurements with a single-electron box (SEB) configured at the edge of the array are used to claim charge sensing of a single quantum dot and of a double quantum dot. The central claim, stated in the abstract, is that this constitutes the first demonstration of controllable formation and coupling of multiple quantum dots together with SEB charge sensing in a commercial process.

Significance. If the interpretation is correct, the paper provides a useful building block for scalable spin-qubit hardware: a commercial CMOS process that can host both a quantum dot array and an integrated charge sensor, without process modifications. The measurements are real, the parameter sweep in VQT1 shows a clear qualitative trend from a double-dot to a merged single-dot response, and the qualitative features in the stability diagrams and bias triangles are consistent with standard double-quantum-dot physics. The paper also describes a concrete reflectometry setup and gives enough terminal definitions to reproduce the biasing scheme. However, the central claim rests almost entirely on visual pattern matching; no quantitative extraction of charging energies, lever arms, tunnel couplings, or dot positions is provided, and the double-dot SEB case is explicitly left unmodeled by the authors themselves.

major comments (3)
  1. [Measurement Results: Quantum Dot Array, Figs. 2 and 3] The interpretation of the stability diagrams as double quantum dot behavior is based on visual similarity to textbook honeycomb diagrams and bias triangle pairs, but no quantitative analysis is presented anywhere in the paper. There is no extraction of charging energies, lever arms, tunnel couplings, or dot-occupation numbers, and no comparison of the data to the companion simulation in ref. 7. This matters because disorder-induced charge traps in an unmodified commercial process can produce honeycomb-like patterns that resemble intentional multi-dot stability diagrams. Since the abstract's claim of controlling the formation and coupling of quantum dots depends on the correctness of the dot assignment, the authors should provide at least one quantitative analysis of a stability diagram (e.g., a fit to a double-dot constant-interaction model or an extracted lever-arm matrix) or otherwise independently confirm the dot interpretation.
  2. [Measurement Results: Single Electron Box, Fig. 4(c)/(f)] The manuscript states, in the paragraph describing the double-dot SEB case, that 'Further analysis is needed to understand each transition in detail in this case and to fit using an appropriate theoretical framework.' This case is one of the two sensing modes claimed in the abstract ('sensing charge transitions in a single- and double quantum dots'), so the headline claim is not quantitatively supported for the double-dot configuration. The reflectometry response is presented only as raw phase and magnitude traces, with no calibration to electron number and no sensitivity or signal-to-noise quantification. To support the claim, the authors should either provide a model fit for the double-dot SEB response or explicitly restrict the central claim to the single-dot sensing mode that is quantitatively understood.
  3. [Abstract and Introduction] The 'for the first time' claim is not benchmarked against ref. 4, which already reports p- and n-type quantum dot arrays manufactured in 22-nm FDSOI CMOS and measured at 2–4 K and 300 K. The authors need to state explicitly what is new relative to ref. 4: for instance, whether the new element is the SEB charge sensing, the bias-triangle transport evidence, or the specific five-gate geometry. Without this comparison, the novelty assertion is not verifiable, and if ref. 4 already demonstrated QD arrays in the same process family, the claim should be revised accordingly.
minor comments (6)
  1. [Measurement Results: Single Electron Box, paragraph after Fig. 4] The text refers to 'Fig. 4(c) and (d)' when describing the triple/double quantum dot SEB configuration, while the Fig. 4 caption describes the double-dot sensing case as panels (c) and (f); the figure reference should be corrected for consistency.
  2. [Abstract] The phrase 'a combination of a back- and gate voltages' is ungrammatical and should read 'a combination of back-gate and gate voltages.'
  3. [References] References 16 and 19 cite the same work (Vigneau et al., Probing quantum devices with radio-frequency reflectometry) and should be merged into a single reference.
  4. [Figure 2 caption] The caption mentions 'blue circles in the side views of the device,' but the side-view insets are not clearly annotated in the figure; please add visible labels or arrows to the figure.
  5. [Measurement Results: Single Electron Box, Fig. 3 caption and text] There is a missing space in 'negativeVDS' in the Fig. 3 caption text, and the sentence 'The barrier in Fig.2(a) is such...' should read 'In Fig. 2(a), the barrier is such...'.
  6. [General] The paper should state the number of measured devices and whether the data are representative or reproducible across multiple cooldowns; as written, all measurements appear to come from a single device, which limits the generality of the 'commercial process' claim.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the central result is an experimental measurement interpreted with standard quantum-dot physics; self-citations point to prior related work, and the admitted unmodeled double-dot SEB case is a limitation, not a circular reduction.

full rationale

This paper reports an experimental characterization of quantum dots in a commercial 22 nm FDSOI process. Its derivation chain is: bias the five-gate device with combinations of back-gate and barrier-gate voltages, measure dc transport and rf reflectometry, and interpret the resulting charge stability diagrams, bias triangles, and SEB responses using standard quantum-dot phenomenology (e.g., refs. 16-18). No parameter is fitted from data and then renamed a prediction; no model output is compared to its own input; and no equation in the paper reduces by construction to a previously assumed result. The self-citations (refs. 7, 9, 10) are pointers to the authors' prior simulations and SEB devices, but the present measured data are independent of those references, and those works are not invoked as a uniqueness theorem or as a way to forbid alternative explanations. The paper explicitly acknowledges that the double-dot SEB sensing case is not quantitatively modeled: "Further analysis is needed to understand each transition in detail in this case and to fit using an appropriate theoretical framework" (Measurement Results: Single Electron Box section, discussion of Fig. 4(c)/(f)). That honest statement marks an evidentiary limitation regarding the interpretation of those transitions, but it is not a circular step. The novelty claim relative to ref. 4 is a factual and historical comparison, not a derivation from the paper's own assumptions. The visual assignment of features to quantum dots is the weakest evidentiary link, but that is a question of confirmation strength, not circularity: the data are external and independent of any model or fit. The derivation is therefore self-contained in the sense relevant to circularity analysis.

Assumptions & free parameters 1 free parameters · 4 assumptions · 0 invented entities

This is an experimental characterization paper with no model fitting. The central interpretation rests on standard quantum dot stability diagram physics and on the authors' prior device simulations; these are domain assumptions rather than ad hoc inventions. The only hand-chosen values are the operating voltages used to demonstrate different coupling regimes.

free parameters (1)
  • Inter-dot barrier voltage VQT1 = 350 mV, 390 mV, 420 mV
    Hand-selected operating points used to demonstrate decoupled, coupled, and merged quantum dot regimes; they are experimental bias settings, not fitted model parameters.
assumptions (4)
  • domain assumption Observed charge stability patterns correspond to electrostatically defined quantum dots
    The interpretation of the grid-like features in Fig. 2 and Fig. 4 as quantum dot charge transitions relies on standard stability diagram theory (refs. 17, 18).
  • domain assumption Bias triangle pairs indicate sequential tunneling through a double quantum dot
    The identification of double dot formation in Figs. 2 and 3 is based on the standard bias triangle signature (refs. 8, 17).
  • domain assumption RF reflectometry phase and magnitude shifts arise from quantum capacitance changes caused by nearby dot charge transitions
    The SEB sensing interpretation relies on rf-reflectometry response models from refs. 16, 18, and 19.
  • domain assumption The voltage configuration forms dots between the polysilicon gates as simulated in prior work
    The operating principle of indirect gate control is taken from the authors' prior modeling paper (ref. 7), not independently derived here.

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Cite this review

Pith. "Pith review of Commercial CMOS Process for Quantum Computing: Quantum Dots and Charge Sensing in a 22 nm Fully Depleted Silicon-on-Insulator Process." pith.science (2026). https://pith.science/paper/6QZU4ISD

@misc{pith2026241208422,
  author       = {Pith},
  title        = {Pith review of: Commercial CMOS Process for Quantum Computing: Quantum Dots and Charge Sensing in a 22 nm Fully Depleted Silicon-on-Insulator Process},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/6QZU4ISD}},
  note         = {Machine review of arXiv:2412.08422}
}
read the original abstract

Confining electrons or holes in quantum dots formed in the channel of industry-standard fully depleted silicon-on-insulator CMOS structures is a promising approach to scalable qubit architectures. In this communication, we present measurement results of a commercial nanostructure fabricated using the GlobalFoundries 22FDX(TM) industrial process. We demonstrate here that quantum dots are formed in the device channel by applying a combination of a back- and gate voltages. We report our results on an effective detuning of the energy levels in the quantum dots by varying the barrier gate voltages in combination with the back-gate voltage. Given the need and importance of scaling to larger numbers of qubits, we demonstrate here the feasibility of single-electron box sensors at the edge of the quantum dot array for effective charge sensing in different operation modes -- sensing charge transitions in a single- and double quantum dots forming the quantum dot array. We also report measurement results demonstrating bias triangle pair formation and precise control over coupled quantum dots with variations in the inter-dot barrier. The reported measurement results demonstrate the ability to control the formation and coupling of multiple quantum dots in a quantum dot array and to sense their charge state via a Single Electron Box sensor in a commercial process for the first time.

Figures

Figures reproduced from arXiv: 2412.08422 by the authors.

Figure 1
Figure 1. (a) 3D view of the five-gate quantum dot array with raised source and drain. The scanning electron microscope (SEM) image of the device shows dummy polysilicon gates that are not included in the 3D view. A backgate terminal is also available in this process but is not visible in this diagram. It connects through a metal VIA to the silicon wafer below the buried oxide. (b) A simplified experimental setup of the measu… view at source ↗
Figure 2
Figure 2. Variation in interdot capacitive coupling and triangle formation with central tunnel barrier. These measurements were taken at 700 mK in transport mode. Quantum dot locations are denoted with blue circles in the side views of the device. (a) Charge stability response for VQT1 = 350 mV. Bias triangle pairs are overlapping and forming at the triple points, showing clear double quantum dot formation. (b) Charge stabili… view at source ↗
Figure 3
Figure 3. Measurements of specific bias triangle pairs at 70 mK. A change in the direction of the triangles is clear with positive and negative VDS. The size of the triangles is also proportional to the magnitude of the applied VDS. (a) and (b) show bias triangle pairs for VDS = +0.5 mV and VDS = −0.5 mV respectively. (c) and (d) show bias triangle pairs for VDS = +0.25 mV and VDS = −0.25 mV respectively. 3/6 [PITH_FULL_IMAG… view at source ↗
Figures from the paper (1 more)
Figure 4
Figure 4. Figure 4: SEB measurement results for three different biasing conditions at 700 mK. (a) and (d) show a large SEB forming between QT0 and QT2, with a quantum dot forming between QT2 and QA1. (b) and (e) show a SEB forming between QT0 and QT1, with a quantum dot forming between QT…

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Forward citations

Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Scalable quantum current source on commercial CMOS process technology

    physics.app-ph 2025-06 conditional novelty 6.0 of 10

    Quantized single-electron pumping is demonstrated in devices fabricated by a commercial 22nm CMOS foundry, with a parallel-pumped current accurate to 1.2e-3 A/A at 50 MHz.

  2. Transport characterization and quantum dot coupling in commercial 22FDX

    cond-mat.mes-hall 2025-01 conditional novelty 6.0 of 10

    Effective mobility screening across six 22FDX process splits selects a thick-oxide NMOS split in which commercial FDSOI qubit arrays show capacitively and tunnel coupled quantum dots along both channel directions.

Reference graph

Works this paper leans on

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