The Ferroelectric Superconducting Field Effect Transistor

Alessandro Paghi; Elia Strambini; Francesco Giazotto; Giorgio De Simoni; Laura Borgongino; Lucia Sorba

REVIEW 3 major objections 4 minor 3 references

The Ferroelectric Superconducting Field Effect Transistor

T0 review · 3 major / 4 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read A Josephson field-effect transistor with a hafnium-oxide gate shows ferroelectric hysteresis at 50 mK and acts as a non-volatile superconducting memory cell that keeps a bit for 24 hours and survives warming above the aluminum critical…

desk verdict A credible cryogenic memory cell with a ferroelectric label that the data do not yet prove. read the letter →

arxiv 2507.04773 v1 pith:AFD7U7UG submitted 2025-07-07 cond-mat.supr-con cond-mat.mes-hallcond-mat.mtrl-sci

Alessandro Paghi , Laura Borgongino , Elia Strambini , Giorgio De Simoni , Lucia Sorba , Francesco Giazotto This is my paper · ORCID

classification cond-mat.supr-concond-mat.mes-hallcond-mat.mtrl-sci PACS 74.50.+r85.25.Cp

keywords ferroelectricityJosephsonfield-effecttransistorhafniumoxideInAsoninsulatorcryogenicmemorynon-volatilehysteresissuperconductingelectronics

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reports a ferroelectric Josephson field-effect transistor made on an InAs-on-insulator platform, with a 30 nm hafnium-oxide gate insulator, measured at 50 mK. Its central claim is that the HfO2 layer acts as a ferroelectric at cryogenic temperatures, so the transistor's switching current and normal-state resistance depend on the history of the gate voltage and remain different at zero gate voltage. The authors use the two resulting states as a non-volatile superconducting single memory cell: one state is a zero-voltage supercurrent-carrying conductor, the other is dissipative. They report state retention for 24 hours and persistence after warming above the critical temperature of the aluminum electrodes. The device also returns to a pristine state when swept with an alternating-sign ambipolar gate routine, and the memory effect only appears once the gate-voltage range exceeds about ±2 V.

What carries the argument

The central mechanism is the remanent polarization of the ALD-grown HfO2 layer, roughly 31 nm thick, placed between the aluminum gate and the InAs channel. According to the paper, a negative remanent polarization at zero gate voltage accumulates electrons in the InAs epilayer, raising the supercurrent and lowering the normal-state resistance; a positive remanent polarization depletes electrons, with the opposite effect. The sign of the remanent polarization is set by the direction from which the gate voltage is swept, and the authors argue that the aluminum gate electrode plays an active role in stabilizing the ferroelectric phase of nominally undoped HfO2, with unintentional doping during ALD not completely ruled out. The ambipolar gating protocol, in which the sign alternates while the magnitude first increases then decreases, erases the polarization history and resets the device.

What would settle it

Measure polarization versus voltage on the same Al/HfO2/InAs gate stack at cryogenic temperature, or run an identical device with a gate metal that does not stabilize the ferroelectric phase; if no ferroelectric P-V hysteresis appears while the transfer hysteresis persists, the central mechanism is not supported.

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Extended reading notes

Core claim

On the paper's own terms, the discovery is that ferroelectricity appears in a superconducting Josephson FET below 1 K: the ALD-grown HfO2 gate insulator on the InAsOI platform shows hysteretic transfer characteristics in both the switching current IS(VGS) and the normal-state resistance RN(VGS), with the hysteresis loop orientation matching n-type ferroelectric behavior rather than charge trapping. Because the hysteresis opens only for gate voltage ranges of at least [-2,2] V, the authors treat the polarization state as programmable: writing at ±3 V and reading at 0 V yields two reproducible states, with IS,0 = 536 ± 8 nA and RN,0 = 41.0 ± 0.3 Ω for state 0, and IS,1 = 33 ± 4 nA and RN,1 = 110.1 ± 1.2 Ω for state 1. The state is non-volatile over 24 hours and survives a thermal cycle to 1.5 K, above the aluminum critical temperature of 1.2 K, because the ferroelectric polarization acts on the carrier density of the InAs channel independently of whether the electrodes are superconducting. The authors further show that an alternating-sign ambipolar gate sweep restores the device to a pristine, non-polarized condition, erasing prior history.

Load-bearing premise

The load-bearing premise is that the hysteresis loop direction observed in IS(VGS) and RN(VGS) is caused by ferroelectric polarization of the HfO2 layer and not by charge trapping, since the paper does not show a direct polarization-voltage loop or a non-ferroelectric control stack.

Editorial extensions

If this is right

A read current chosen between IS,1 and IS,0 makes state 0 a zero-voltage non-dissipative path and state 1 a resistive dissipative path, so the stored bit can be sensed directly as a voltage.
Since the hysteresis peak sits near 0 V, the device can be written at ±3 V and read at 0 V, cutting the read voltage in half and lowering read energy.
The state survives continuous readout for 24 hours and a warm-up to 1.5 K, so the memory cell tolerates temperature oscillations and cryostat failures without losing data.
If the read current is kept below IS,1, both encoded states are non-dissipative and differ in Josephson inductance, 0.6 nH versus 10.0 nH, allowing an AC inductive readout with zero active power under the paper's linear inductance model.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

A direct polarization-voltage measurement on the same HfO2 stack at 50 mK would be the natural next step; until that is shown, trapped charge at the InAs/HfO2 interface remains a possible alternative explanation for the observed hysteresis loop orientation.
If the ferroelectric assignment holds, engineering the HfO2 with silicon or zirconium doping, which the authors mention as future work, could increase the remanent polarization and make the write voltages lower and the hysteresis window wider.
The write-read voltage asymmetry suggests a memory array design where the write word-line voltage is higher than the read voltage, but the paper does not demonstrate array-level operation or cross-talk behavior.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Colleague,

The memory cell is probably real; the ferroelectric mechanism is not yet proven. If you work on cryogenic memory or hybrid superconducting electronics, pay attention to the device demonstration. If you are reading for hafnium ferroelectricity, this paper won't convince you.

What is actually new: first Josephson FET with a ferroelectric gate insulator. The authors show hysteresis in switching current and normal-state resistance as the gate range grows, two stable states at VGS=0 over 10 write/read cycles (CV ~12%), 24 h retention, and state survival through a thermal cycle above Al Tc. The ambipolar reset protocol is a useful practical addition. The inductive readout is a standard LJ = hbar/(2e IS) estimate, no back-fitting; IREAD is just a chosen bias.

The soft spot is load-bearing and the manuscript itself flags it. The ferroelectric claim rests on the orientation of the hysteresis loop. There is no P-V loop, no structural phase identification, and no matched control device with a non-ferroelectric gate stack. The text says trapping would give the opposite trend, then two paragraphs later says 'thanks to the charge trapping activated by positive VGS values...' while describing the observed depletion. That is the trapping mechanism they just excluded. They also concede unintentional ALD doping cannot be ruled out. The prior observation that Al gates are needed for ferroelectricity in their ALD HfO2 is referenced, not shown here. So the memory function and thermal stability stand, but they are equally consistent with trapped charge or ion motion. Add single-device data, and the mechanism is under-supported, not disproved. The citation pattern is fine; the self-citations to the InAsOI platform and prior JoFET work are appropriate.

Who this is for: groups working on cryogenic memory architectures and gate-programmable superconducting electronics. It deserves a serious referee, with a clear request for direct polarization or structural evidence, a control device, and reproducibility across devices. Conditional acceptance is the right call; the engineering is solid, the physics claim needs one more round of experiments.

Referee Report

3 major / 4 minor

Summary. The paper reports a Josephson FET fabricated on the InAsOI platform with a 30-nm ALD-grown HfO2 gate insulator. The device exhibits hysteresis in the switching current IS and normal-state resistance RN as a function of gate voltage VGS, which the authors attribute to ferroelectric polarization of the HfO2 layer. They demonstrate that the hysteresis can be controlled by the VGS range and that the device can be reset to a pristine state by an ambipolar gating protocol. They then operate the device as a cryogenic superconducting single memory cell, with two states defined by write pulses at ±3 V and read at 0 V, showing reproducible readouts over 10 cycles, retention for 24 h, and survival of a warm-up to 1.5 K (above Al Tc). They also propose a fully non-dissipative readout scheme based on the difference in Josephson inductance between the two states.

Significance. The manuscript addresses an important gap: cryogenic non-volatile memories compatible with superconducting circuits. The memory demonstrations are well-executed: clear hysteresis, reproducibility, 24-h retention, and thermal cycling are all presented with quantitative state values and variation estimates. The device concept (ferroelectric gate on a Josephson FET) is novel if the ferroelectric interpretation holds. However, the central mechanistic claim rests on indirect evidence, and the manuscript contains an internal inconsistency in which charge trapping is invoked in the same section that argues for ferroelectricity. If the authors can provide direct structural or electrical evidence of ferroelectricity (P-E loops, PFM, GIXRD) or a matched control experiment, this would be a significant contribution. The paper is clearly written and the experimental methods are described in sufficient detail to be reproduced.

major comments (3)

[Results and Discussion, Figure 2 discussion] The text states 'thanks to the charge trapping activated by positive VGS values, the depletion of electrons from the InAs epilayer into interfacial traps results in a reduced switching current and increased normal-state resistance during the downward VGS scan.' This sentence explicitly describes charge trapping as the operative mechanism, directly contradicting the ferroelectric interpretation given elsewhere in the same paragraph and in the abstract. This internal inconsistency is load-bearing: if charge trapping controls the hysteresis, the ferroelectric claim is unsupported. Please resolve whether the mechanism is ferroelectric polarization or trapped charge, or provide evidence distinguishing the two.
[Results and Discussion, Figures 1 and S1] The identification of ferroelectricity is based solely on the orientation of hysteresis in IS(VGS) and RN(VGS) compared to a schematic (Figure S1b). No direct polarization–electric field measurement, structural phase analysis (e.g., GIXRD or PFM), or matched control device without a ferroelectric gate stack is presented. The statement that ALD-grown HfO2 in this chamber is ferroelectric without intentional doping when capped with Al is an assertion; the comparison with Au or Ti/Al gates refers to previous work (refs [26,29]), not to control devices in this study. Because charge trapping or mobile ions can produce the same hysteresis, retention, and thermal cycling behavior, the central mechanistic claim is under-supported as presented.
[Results and Discussion, Figure 2 discussion] The paper concedes that 'unintentional doping during the ALD process cannot be completely ruled out.' This admission, combined with the lack of direct structural evidence, means the reproducibility and generality of the ferroelectric phase in this stack are not established. At minimum, the text should either present evidence that the observed behavior is ferroelectric or temper the abstract and conclusions accordingly (e.g., 'hysteresis consistent with ferroelectric-like behavior').

minor comments (4)

[Figure 1d caption] In the caption, 'block dots' should be 'black dots'.
[Abstract and Introduction] The phrase 'we observed ferroelectricity' is used in the abstract and introduction; given that the evidence is indirect and contested in the text, this should be rephrased to 'hysteresis consistent with ferroelectric behavior' unless direct evidence is added.
[Results and Discussion, Figure 4] In the memory operation, state 1 is dissipative because the read current IREAD is chosen between IS,0 and IS,1 (IREAD = (IS,0 + IS,1)/2), not because the device itself is dissipative in that state. The text should clarify that the dissipative/non-dissipative distinction is a readout choice, and that both states can be non-dissipative if IREAD < IS,1.
[Conclusions, inductive readout proposal] The Josephson inductance calculation assumes IREAD << IS,1, but the earlier readout uses IREAD = (IS,0 + IS,1)/2, which is not small compared to IS,1. The relationship between the two operating regimes should be stated to avoid confusion about the validity of the inductance formula.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the device metrics are direct measurements or standard formulas, and the ferroelectric attribution is an under-supported inference rather than a derivation that reduces to its own inputs.

full rationale

The paper's central quantities are obtained by direct measurement or by standard, externally grounded formulas, not by fitting a parameter and then predicting that same parameter. The switching current and normal-state resistance are measured transfer characteristics; the Josephson inductance values are computed from the measured switching current via the standard relation L_J = hbar/(2 e I_S); and the memory readout is a direct voltage measurement across the device. The ferroelectric interpretation is inferred from the orientation of the hysteresis loops and from prior reports on HfO2, which is an evidentiary argument rather than a circular one. The self-citations to refs [25,26,29] concern the InAsOI platform, dielectric characterization, and previous JoFET devices; these are independent published measurements and are not used to assume the target result. The manuscript does contain an evidentiary weakness and an internal inconsistency: the ferroelectric mechanism is asserted without a direct polarization-voltage loop or control device, and the text includes the sentence 'thanks to the charge trapping activated by positive VGS values, the depletion of electrons from the InAs epilayer into interfacial traps results in a reduced switching current and increased normal-state resistance during the downward VGS scan,' which conflicts with the earlier exclusion of charge trapping. However, this is a support or correctness concern, not a circular derivation. No step in the claimed derivation chain is equivalent to its own input by construction, so the circularity score is 0.

Assumptions & free parameters 1 free parameters · 4 assumptions · 0 invented entities

The memory operation depends on empirically chosen operating points (gate voltages, read current) and on the assumption that the observed hysteresis is a ferroelectric signature. No new physical entities are introduced. The ferroelectric mechanism is inferred, not directly measured.

free parameters (1)

IREAD = (IS,0 + IS,1)/2 ≈ 284 nA
Read current chosen by hand as the midpoint between the two switching currents (536 nA and 33 nA) so that state 0 is non-dissipative and state 1 is dissipative. The memory readout protocol is defined relative to this value.

assumptions (4)

domain assumption The direction of hysteresis (counterclockwise in IS, clockwise in RN) is unique to ferroelectric polarization in an n-type FeFET.
Used to attribute the memory effect to ferroelectricity; alternative mechanisms such as charge trapping are argued to produce the opposite trend, but no quantitative control comparison on the same device is shown in the main text (Figure S1 is referenced only).
ad hoc to paper ALD-grown HfO2 in this chamber is ferroelectric without intentional doping when capped with Al, and the Al gate chemically stabilizes the ferroelectric phase.
The paper states 'HfO2 films grown by ALD in our chamber exhibited ferroelectric behavior even without intentional doping, but only when paired with a pristine Al gate' and 'suggests a chemically active role of the Al gate... possibly through interfacial interactions or diffusion.' No direct structural or polarization evidence is provided in this work.
standard math The standard Josephson inductance formula LJ = hbar/(2eIS) applies to the Fe-JoFET.
Used in the proposed fully non-dissipative readout section to compute expected inductance values; a textbook result assumed to hold for the proximitized InAs junction.
domain assumption The InAsOI substrate is electrically insulating below 70 K.
Relies on prior characterization (ref [25]) to ensure gate action is not shunted by the substrate; taken as input from the authors' earlier publication.

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Cite this review

Pith. "Pith review of The Ferroelectric Superconducting Field Effect Transistor." pith.science (2026). https://pith.science/paper/AFD7U7UG

@misc{pith2026250704773,
  author       = {Pith},
  title        = {Pith review of: The Ferroelectric Superconducting Field Effect Transistor},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/AFD7U7UG}},
  note         = {Machine review of arXiv:2507.04773}
}

read the original abstract

The ferroelectric field-effect transistor (Fe-FET) is a three-terminal semiconducting device first introduced in the 1950s. Despite its potential, a significant boost in Fe-FET research occurred about ten years ago with the discovery of ferroelectricity in hafnium oxide. This material has been incorporated into electronic processes since the mid-2000s. Here, we observed ferroelectricity in a superconducting Josephson FET (Fe-JoFET) operating at cryogenic temperatures below 1 Kelvin. The Fe-JoFET was fabricated on the InAsOI platform, which features an InAs epilayer hosted by an electrical insulating substrate, using HfO2 as the gate insulator, making it a promising candidate due to its ferroelectric properties. The Fe-JoFET exhibits significant hysteresis in the switching current and normal-state resistance transfer characteristics, which depend on the range of gate voltages. This phenomenon opens a new research area exploring the interaction between ferroelectricity and superconductivity in hybrid superconducting-semiconducting systems, with potential applications in cryogenic data storage and computation. Supporting this, the Fe-JoFET was operated as a cryogenic superconducting single memory cell, exhibiting both dissipative and non-dissipative states. Its non-volatility was tested over a 24-hour measurement period. We also demonstrated that the Fe-JoFET can retain information at temperatures above the superconductor critical temperature, resulting in a temperature-fault-tolerant memory cell resistant to temperature oscillations or, in the worst case, cryostat faults.

Figures

Figures reproduced from arXiv: 2507.04773 by the authors.

**Figure 1.** Ferroelectric hysteresis in the InAsOI-based Josephson Field Effect Transistor. a) 3D and b) cross-sectional views of an InAsOI-based JoFET. c) Voltage versus current curve of the InAsOI-based JoFET at VGS = 0 V during both downward (top) and upward (bottom) VGS scans. d) Switching current (top) and normal-state resistance (bottom) versus gate voltage transfer [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗

**Figure 2.** Ferroelectricity at work in the InAsOI-based JoFET. Microscopic sketch to explain how the gate insulator ferroelectricity acts on the JoFET electrical performance. a) Increasing the gate electric field from negative values results in a negative remanent polarization of the insulator at zero electric field, with the consequent enhancement of electrons in the InAs semiconducting layer, which can contribute to the supe… view at source ↗

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Reference graph

Works this paper leans on

3 extracted references · 3 canonical work pages

[1]

O. Arif, L. Canal, E. Ferrari, C. Ferrari, L. Lazzarini, L. Nasi, A. Paghi, S. Heun, L. Sorba, Influence of an Overshoot Layer on the Morphological, Structural, Strain, and Transport Properties of InAs Quantum Wells, Nanomaterials. 14 (2024) 592. https://doi.org/10.3390/nano14070592

work page doi:10.3390/nano14070592 2024
[2]

Paghi, G

A. Paghi, G. Trupiano, G. De Simoni, O. Arif, L. Sorba, F. Giazotto, InAs on Insulator: A New Platform for Cryogenic Hybrid Superconducting Electronics, Adv. Funct. Mater. 35 (2025). https://doi.org/10.1002/adfm.202416957

work page doi:10.1002/adfm.202416957 2025
[3]

Paghi, S

A. Paghi, S. Battisti, S. Tortorella, G. De Simoni, F. Giazotto, Cryogenic behavior of high- permittivity gate dielectrics: The impact of atomic layer deposition temperature and the lithographic patterning method, J. Appl. Phys. 137 (2025). https://doi.org/10.1063/5.0250428

work page doi:10.1063/5.0250428 2025

Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.

[1] [1]

O. Arif, L. Canal, E. Ferrari, C. Ferrari, L. Lazzarini, L. Nasi, A. Paghi, S. Heun, L. Sorba, Influence of an Overshoot Layer on the Morphological, Structural, Strain, and Transport Properties of InAs Quantum Wells, Nanomaterials. 14 (2024) 592. https://doi.org/10.3390/nano14070592

work page doi:10.3390/nano14070592 2024

[2] [2]

Paghi, G

A. Paghi, G. Trupiano, G. De Simoni, O. Arif, L. Sorba, F. Giazotto, InAs on Insulator: A New Platform for Cryogenic Hybrid Superconducting Electronics, Adv. Funct. Mater. 35 (2025). https://doi.org/10.1002/adfm.202416957

work page doi:10.1002/adfm.202416957 2025

[3] [3]

Paghi, S

A. Paghi, S. Battisti, S. Tortorella, G. De Simoni, F. Giazotto, Cryogenic behavior of high- permittivity gate dielectrics: The impact of atomic layer deposition temperature and the lithographic patterning method, J. Appl. Phys. 137 (2025). https://doi.org/10.1063/5.0250428

work page doi:10.1063/5.0250428 2025