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REVIEW 2 major objections 6 minor 36 references

Under a one-megabyte activation budget, a compact int8 CNN with F-Clip encoding can reach sAP10 of 24.1 for line segments on microcontrollers.

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2026-07-11 03:21 UTC pith:KBUWTMRJ

load-bearing objection First careful accuracy–memory map for learned line detection under real MCU SRAM; clean ablations, deferred silicon numbers, no circularity. the 2 major comments →

arxiv 2607.06600 v1 pith:KBUWTMRJ submitted 2026-07-07 cs.CV cs.AIcs.RO

MiLSD: A Micro Line-Segment Detector for Resource-Constrained Devices

Parsa Hassani Shariat Panahi , Amir Hossein Jalilvand , M. Hassan Najafi This is my paper
classification cs.CV cs.AIcs.RO
keywords line segment detectionTinyMLquantizationmemory-constrained inferenceembedded visionF-ClipMCUwireframe parsing
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Learned line-segment detectors have been accurate only on phones and GPUs, while classical detectors fit tiny hardware but pick up every edge. This paper asks how much structural accuracy is possible when peak activation memory is capped below one megabyte. It shows that a center-length-angle encoding learns far better than heatmaps or endpoint offsets at tiny model sizes, that 8-bit quantization preserves full-precision quality while 4-bit does not, and that sub-pixel decoding, flip averaging, and a small verification head can lift a 25k-parameter baseline from sAP10 of 10.6 to 24.1 once the budget grows to roughly 1 MB. The point is not to beat GPU parsers; it is to chart the real accuracy–memory frontier so embedded vision systems can place a learned wireframe detector on low-cost MCUs.

Core claim

At extreme memory limits the choice of output representation dominates capacity: the F-Clip formulation (center confidence, length, and double-angle orientation) is the only encoding that yields coherent segments with a 25k-parameter fully-convolutional backbone. Eight-bit quantization preserves that performance; four-bit quantization collapses angle regression even under quantization-aware training. Scaling the same backbone to a ~1 MB activation arena and adding only inference-time refinements (sub-pixel peaks, four-view TTA, and a lightweight Line-of-Interest verifier) raises sAP10 on ShanghaiTech Wireframe from 10.6 to 24.1, placing the first learned line detector inside microcontroller

What carries the argument

F-Clip center-with-length-and-angle encoding: each segment is a center peak plus length and (cos 2θ, sin 2θ) on a 128×128 grid, decoded by peak NMS and optional sub-pixel fit, then re-scored by a tiny Line-of-Interest MLP that pools features along the candidate.

Load-bearing premise

The claim that the whole pipeline stays inside roughly 1 MB of real STM32H7 SRAM and runs usefully rests on software-measured activation arenas that the paper itself says still need on-device confirmation.

What would settle it

Export the exact int8 MiLSD graph through the vendor tool chain, flash it on a bare STM32H7, and measure peak SRAM occupancy together with Wireframe sAP10; if peak memory exceeds the 1 MB envelope or accuracy falls well below 24.1, the central resource claim fails.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • F-Clip-style geometric heads should be the default starting point for any new sub-megabyte line detector.
  • Int8 is a safe deployment target; sub-8-bit designs for angle regression need new encodings or training methods.
  • Accuracy can be roughly doubled after training by memory-neutral post-processing (sub-pixel, TTA, small verifier) without enlarging the stored network.
  • The previously empty MCU column in the line-detector table is now occupied, so future TinyML geometric work has a concrete accuracy–memory reference curve.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Angle and other continuous geometric heads may systematically demand higher bit-width than classification maps in TinyML vision, so mixed-precision or specialized encodings for orientation could be the next lever.
  • The same three-axis map (representation, bit-width, post-processing) can be reused for other sparse geometric primitives—junctions, vanishing points, or short arcs—on the same MCU class.
  • Classical edge walkers may still win pure latency contests; MiLSD defines a learned niche rather than a universal replacement.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 6 minor

Summary. The paper studies line-segment detection under sub-megabyte MCU memory budgets. It compares three output encodings (heatmap, center+displacement, F-Clip center+length+double-angle) on a compact fully-convolutional backbone, shows that F-Clip is most effective at ~25k parameters (sAP10=10.6 on ShanghaiTech Wireframe), and reports that int8 quantization preserves fp32 accuracy while int4 collapses especially on the (cos2θ,sin2θ) head, with QAT only partially recovering. Scaling the backbone to ~0.39M parameters under a ~1 MB activation arena and adding sub-pixel decoding, 4-view TTA, and a frozen-backbone Line-of-Interest verifier yields MiLSD at sAP10=24.1. The work positions itself as an accuracy–memory map for embedded vision rather than a competitor to GPU parsers, and releases code.

Significance. If the reported trade-offs hold, the paper fills a previously empty MCU column in the line-detection literature: no prior learned detector is evaluated under sub-megabyte SRAM with an int8/int4 study. The representation ablation (heatmap 0.3 → endpoint 3.6 → F-Clip 10.6 at fixed 25k params), the angle-head sensitivity to 4-bit quantization, and the staged inference gains (17.8 → 18.1 → 21.0 → 24.1) are concrete, falsifiable engineering results on the standard Wireframe split and sAP metric. Released code and the explicit accuracy–resource frontier (Table IV, Fig. 9) are genuine strengths for TinyML geometric vision. The absolute accuracy remains far below GPU parsers, which the authors correctly treat as a regime limit rather than a failure.

major comments (2)
  1. Section V-E states that on-device arena and latency 'must be confirmed with ST Edge AI' and reports only software-measured peaks (~1 MB activation arena, ~0.54 MB weights). The central claim is an accuracy–memory map under a 1 MB budget on STM32H7; without measured peak SRAM, wall-clock FPS, and power on silicon (or an explicit X-CUBE-AI arena dump), the binding constraint remains unverified. This does not invalidate the sAP or quantization results, but it is load-bearing for the deployment claim and should be closed or clearly demoted to a software estimate.
  2. Table V and Section V-C: the LoI verifier is trained with the backbone frozen and contributes the largest single gain (+3.1 sAP10). The paper does not report an ablation of verifier capacity, pooling density (32 points), or training labels (one-to-one matching), nor whether the verifier was quantized to int8 with the backbone. Because the 24.1 figure is the headline MiLSD number, a short sensitivity check or confirmation that the head fits inside the same arena under int8 is needed to make the staged gains fully reproducible.
minor comments (6)
  1. Abstract and Section IV-A: the abstract says F-Clip reaches 10.6 at 25k params, while the narrative climb in IV-A first quotes 7.2 then 10.6 after data/aug/epochs; a single consistent baseline number in the abstract and Fig. 5 caption would avoid confusion.
  2. Fig. 5 y-axis and caption: the progression mixes representation changes with capacity and post-processing; labeling which bars share the same backbone width would make the representation-only claim clearer.
  3. Table III: heatmap row notes that sAP is not the right metric and reports Q2/recall instead; either move heatmap to a separate classical-style evaluation or drop sAP for that row entirely to avoid mixing metrics.
  4. Section II-A: the double-angle encoding is well motivated, but the loss weighting (2.0 on geometric terms) and masking are only in Table II; a one-sentence justification in the text would help.
  5. Fig. 9 / Table IV: parameter counts for prior work are taken from LINEA and papers; a footnote that some counts are approximate (e.g., HAWPv2 ~11M) would be more precise.
  6. Typos / polish: 'improvessAP' (abstract), 'On MCU?' column consistency, and a few missing spaces around sAP subscripts in the text.

Circularity Check

0 steps flagged

No circularity: accuracy claims are empirical ablations on an external benchmark, not predictions forced by construction or self-citation.

full rationale

MiLSD is an engineering systems paper that maps accuracy–memory trade-offs for MCU-scale line-segment detection. Its load-bearing claims (F-Clip best at ~25k params, int8 preserves fp32, int4 angle-head fragility, capacity scaling to ~0.39M params, staged gains from sub-pixel/TTA/LoI to sAP10=24.1) are all measured against the external ShanghaiTech Wireframe ground truth with the community sAP metric. Representation choice, bit-width, width scaling, and post-processing stages are ablated against that fixed held-out set; none of the reported sAP figures is a fitted free parameter renamed as a prediction, nor does any central result reduce by definition to its inputs. Self-references are limited to the authors’ own design-search notebooks and released code for reproducibility; they do not supply uniqueness theorems or load-bearing premises. The paper does not claim first-principles derivation of geometry or uniqueness of the F-Clip encoding; it reports empirical comparison. Hardware-arena confirmation is deferred (Section V-E) but that is a measurement gap, not circularity. Score 0 is therefore the correct outcome.

Axiom & Free-Parameter Ledger

5 free parameters · 4 axioms · 1 invented entities

The central claims rest on standard supervised-learning and quantization practice plus the empirical Wireframe benchmark; almost no new mathematical axioms or invented physical entities are introduced. Free parameters are ordinary training and architecture choices (channel widths, loss weight 2.0, 300 epochs, confidence thresholds, 32-point LoI pooling). The only domain assumptions are that sAP on Wireframe is a meaningful proxy for embedded utility and that CMSIS-NN/X-CUBE-AI faithfully realize the claimed memory envelope.

free parameters (5)
  • backbone channel widths (8→16→32→32→32 and width-4 scaling to ~0.39 M)
    Chosen by hand to stay under the target activation arena; not derived from first principles.
  • geometric loss weight 2.0
    Hand-set multiplier on smooth-L1 length/angle terms relative to BCE center loss (Table II).
  • training schedule (300 epochs, Adam 1e-3 cosine, batch 32)
    Standard but free hyper-parameters that affect the final sAP numbers.
  • LoI pooling (32 bilinear samples) and verification MLP size
    Architecture choices that determine how much of the oracle gap is recovered.
  • center-confidence and verification score thresholds / NMS
    Inference-time free parameters that control precision-recall operating point.
axioms (4)
  • domain assumption ShanghaiTech Wireframe sAP at squared-endpoint thresholds is a valid proxy for embedded line-detection quality.
    Used throughout Sections III–V as the sole accuracy metric; no alternative real-world MCU dataset is provided.
  • domain assumption Per-tensor symmetric int8/int4 quantization with STE approximates the deployed CMSIS-NN kernels.
    Section II-C; standard TinyML assumption but not re-validated on the target silicon in the paper.
  • standard math Double-angle (cos 2θ, sin 2θ) uniquely encodes undirected line orientation.
    Section II-A; elementary trigonometry used to remove the 180° ambiguity.
  • domain assumption Peak activation memory, not parameter storage, is the binding SRAM constraint on the target MCUs.
    Stated in Introduction and Section II; drives the entire design.
invented entities (1)
  • MiLSD (the full H7 pipeline with LoI verifier) no independent evidence
    purpose: Name for the capacity-scaled F-Clip detector plus sub-pixel, TTA, and learned verification stages that together reach sAP10=24.1 inside 1 MB.
    System-level composition of known components; no new physical or mathematical object is postulated.

pith-pipeline@v1.1.0-grok45 · 19576 in / 3169 out tokens · 26337 ms · 2026-07-11T03:21:49.900037+00:00 · methodology

0 comments
read the original abstract

Line segment detection is a key building block in visual SLAM, 3D reconstruction, and industrial inspection. Recent deep learning methods have greatly improved accuracy, yet even the smallest models require several megabytes of memory, exceeding low-cost MCU capacity. This work investigates the maximum achievable accuracy under a sub-megabyte budget. We propose MiLSD, a detector tailored for MCU-level constraints, and systematically compare three output representations within a compact fully-convolutional backbone. Our study shows that the proposed F-Clip center-with-length-and-angle formulation learns most effectively at small model sizes. We find that 8-bit quantization preserves full-precision performance, while 4-bit quantization causes significant degradation, particularly in angle regression, with quantization-aware training recovering only part of the loss. With a one-megabyte activation budget and inference enhancements including sub-pixel decoding, test-time augmentation, and a lightweight verifier, MiLSD improves sAP10 on ShanghaiTech Wireframe from 10.6 (25k parameters, 0.25 MB) to 24.1 within 1 MB. Rather than competing with GPU-scale parsers, we map the accuracy memory trade-off across representations, bit-widths, capacities, and post-processing strategies for embedded vision systems.

Figures

Figures reproduced from arXiv: 2607.06600 by Amir Hossein Jalilvand, M. Hassan Najafi, Parsa Hassani Shariat Panahi.

Figure 2
Figure 2. Figure 2: Backbone and output head architecture. A [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Quantization scheme. Continuous weights are snapped to discrete [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Off-device training and on-MCU inference pipeline. The model is trained on GPU with quantization simulation, then exported through X-CUBE-AI [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: From baseline to MiLSD: sAP10 on Wireframe at each step. The output representation drives the first gains (heatmap v1 → endpoint v2 → F-Clip), reaching 10.6 for the 25k-parameter F-Clip model; scaling capacity to the width-4 MiLSD backbone (0.39 M parameters) lifts this to 17.8, and the inference-time stages (test-time augmentation then the Line-of-Interest verification head) carry it to sAP10 = 24.1 (purp… view at source ↗
Figure 6
Figure 6. Figure 6: sAP10 versus bit-width for the deployed F-Clip model on Wireframe. The int8 point overlaps fp32; PTQ at 4 bits fails while QAT partially recovers. a meaningful structural score, reaching sAP10 = 3.6, yet it remains limited in its ability to recover coherent geometry. The decisive inflection occurs with the adoption of the F-Clip representation, which at the identical 25k-parameter budget more than doubles … view at source ↗
Figure 7
Figure 7. Figure 7: Input resolution sets a genuine accuracy–memory trade-off. Accuracy [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Training the F-Clip model over 300 epochs. Train and held-out loss [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Accuracy vs. parameter budget on the Wireframe benchmark (log-scale [PITH_FULL_IMAGE:figures/full_fig_p006_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Detections on two Wireframe-val images for v1 (heatmap), v2 (endpoint), and v3–v6 (F-Clip progression); layout described in Section IV-F. The [PITH_FULL_IMAGE:figures/full_fig_p007_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: MiLSD inference pipeline on the STM32H7. An int8 fully-convolutional backbone predicts F-Clip center/length/angle maps; candidate segments are [PITH_FULL_IMAGE:figures/full_fig_p008_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Four Wireframe-val scenes: ground truth (left, green) and MiLSD [PITH_FULL_IMAGE:figures/full_fig_p009_12.png] view at source ↗

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    His research interests include stochastic and approxi- mate computing, unary processing, in-memory com- puting, and hyperdimensional computing

    He is currently an Associate Professor at the Electrical, Computer, and Systems Engineering Department at Case Western Reserve University. His research interests include stochastic and approxi- mate computing, unary processing, in-memory com- puting, and hyperdimensional computing. He has authored/coauthored more than 120 peer-reviewed papers and has been...

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