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A graph-based Bayesian optimizer discovers compact quantum circuits that match or beat flat-feature search on a real classification task.

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A graph-neural-network-guided Bayesian search discovers compact variational quantum circuits for a cybersecurity classification task, slightly beating a flat-feature MLP surrogate and dominating fixed-architecture baselines.

T0 review reviewed 2026-08-03 challenge →

load-bearing objection A genuinely new combination — GIN surrogate with MC-dropout uncertainty inside a cost-tempered BO loop for VQC search — worth refereeing, but the 'all baselines' complexity claim outruns the evidence and the evaluation needs error bars and a fairer baseline setup. the 3 major comments →

arxiv 2512.09586 v2 pith:KGP47NWQ submitted 2025-12-10 quant-ph cs.AIcs.LGcs.NEcs.NI

Graph-Based Bayesian Optimization for Quantum Circuit Architecture Search with Uncertainty Calibrated Surrogates

Prashant Kumar Choudhary , Nouhaila Innan , Muhammad Shafique , Rajeev Singh This is my paper
classification quant-ph cs.AIcs.LGcs.NEcs.NI
keywords quantum circuit architecture searchBayesian optimizationgraph neural networksvariational quantum circuitsuncertainty calibrationMonte Carlo dropouthybrid quantum-classical classificationnoise robustness
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper argues that representing variational quantum circuits as graphs and learning a graph neural network surrogate with Monte Carlo dropout lets Bayesian optimization discover circuit architectures that are both more accurate and less complex than those found by flat-feature surrogates, random search, or greedy selection. On a balanced cybersecurity classification task (NF-ToN-IoT-V2), the graph-guided loop finds circuits with higher test accuracy at 10 and 12 qubits and consistently lower gate counts and depth. The authors also show the discovered circuits retain accuracy under several noise channels, with depolarizing noise the main exception. If correct, the work offers a practical route to automating VQC design for near-term quantum hardware.

Core claim

The central claim is that a Bayesian optimization loop whose surrogate is a graph isomorphism network (GIN) trained on circuit graphs—with Monte Carlo dropout supplying epistemic uncertainty—can rank mutated VQC candidates accurately enough that expected improvement yields better circuits in fewer true evaluations than MLP, random, or greedy baselines, and the circuits it returns are shallower and sparser while achieving competitive or better classification accuracy. The authors report test accuracies of 94.25% at 12 qubits for their method versus 92.95% for the MLP surrogate and about 83% for random/greedy, with lower two-qubit counts and depth. They attribute this to the graph encoding pre

What carries the argument

The central object is the circuit graph: each gate is a node with one-hot type, temporal position, qubit incidence, and two-qubit flag; edges encode temporal adjacency, shared-qubit connectivity, and per-qubit sequential links. A two-layer GIN (hidden width 128, dropout 0.3) trained by MSE to predict validation accuracy provides the predictive mean and, via 30 MC-dropout passes, the epistemic variance. The acquisition is expected improvement (Eq. 19) tempered exponentially by a normalized cost of depth, two-qubit count, CZ count, total gates, and a decoherence proxy (Eqs. 20-22, 16). This structure-aware, uncertainty-calibrated scoring is what steers the mutation-based search toward compact,

Load-bearing premise

The GIN surrogate's predictive mean and MC-dropout variance, trained only on the 50 initial circuits plus in-loop evaluations, generalize well enough to rank structurally novel mutated circuits correctly; if this ranking degrades on out-of-sample circuits, especially in early iterations, the acquisition collapses to noise and the claimed advantage over the MLP surrogate disappears.

What would settle it

Run the same BO loop but replace the GIN surrogate's acquisition scores with random rankings (or with an MLP) while keeping all other settings identical; if the GNN's advantage over random search vanishes, the claim that structure-aware ranking drives the improvement is falsified. More directly, evaluate the GIN's Kendall tau against true validation accuracy on a held-out set of 1000 randomly mutated circuits never seen during BO; a tau at or below zero would contradict the ranking-fidelity claim.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • Circuit architecture search for VQCs can be automated without hand-designed ansätze; the search space is graph mutations over a gate set.
  • Structure-aware surrogates (GNNs) can beat flat-feature surrogates on ranking fidelity (Kendall tau) and final test accuracy, especially at larger qubit counts (12 qubits).
  • Cost-tempered acquisition penalizing depth and two-qubit gates shifts found circuits onto a Pareto frontier where extra complexity yields diminishing returns.
  • Noise robustness: circuits found under cost/noise-aware search retain roughly 85-87% test accuracy under amplitude, thermal, and readout noise, with depolarizing noise the most damaging.
  • The method is computationally feasible: surrogate overhead is negligible relative to VQC training, so wall-clock is dominated by circuit evaluation.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The graph representation's advantage likely grows with search-space size; at 8 qubits the gap is small, at 12 it is clear, so one might expect even larger gains for higher qubit counts or richer gate sets.
  • The MC-dropout uncertainty calibration could be replaced by deep ensembles or other Bayesian approximations; the paper's core claim does not depend on this specific choice, only on having ranking-usable uncertainty.
  • A direct testable extension would be to use the same BO loop to find circuits for other datasets or hardware topologies, since the pipeline is modular—swap the feature selection, choose a backend, and rerun.
  • The noise robustness results suggest that mild amplitude or thermal damping acts as a regularizer for angle-embedded features; this could be probed further by varying noise strength and measuring overfitting metrics.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes a Bayesian optimization framework for variational quantum circuit architecture search in which candidate circuits are encoded as graphs and scored by a GIN surrogate with MC-dropout uncertainty; acquisition is expected improvement tempered by a complexity cost. The pipeline is evaluated on an NF-ToN-IoT-V2 binary classification task for 8, 10, and 12 qubits against an MLP surrogate, a greedy GNN selector, and random search, with additional noise-robustness sweeps. The central claim is that the GNN-guided optimizer consistently finds lower-complexity circuits with competitive or superior accuracy compared to all baselines.

Significance. If the central claim held, the paper would make a useful empirical contribution: it combines graph-structured circuit representation, an uncertainty-aware GNN surrogate, and cost-aware acquisition in a single end-to-end pipeline, with a credible effort toward reproducibility (code release, exported circuits, calibration and ranking metrics). The DAG encoding and MC-dropout uncertainty estimation are sensible and potentially transferable. However, the headline result is currently not supported by the paper's own data, the central comparisons rest on single runs without error bars, and the advertised hardware-aware mapping component is explicitly disabled in all experiments. These are load-bearing issues that require substantive revision before the claims can be accepted.

major comments (3)
  1. [Tables 2–3 and Figs. 5–12] All reported accuracies, convergence curves, ranking metrics, and complexity comparisons appear to come from single runs, with no seeds, error bars, or significance tests. Given the stochastic mutation kernel, MC-dropout, and neural-network training, differences such as Q=10 test accuracy of 89.20% (Table 2) versus 90.10%/93.20% for Mut=5/10 (Table 3) may be within run-to-run noise. The word 'consistently' in the abstract and Sec. 4.5 is therefore not supported. At minimum, the experiments should be repeated with several random seeds (e.g., 5–10) and reported as mean ± standard deviation, with pairwise significance tests for the main comparisons. This is a load-bearing issue for the central empirical claim.
  2. [§3.3, Eq. (20) and Appendix A.1] The paper advertises 'hardware-realistic optimization' and 'transpiler-aware selection' as a contribution, but the actual acquisition used in all experiments has mapped cost disabled. Eq. (20) defines C_total = C_base + C_map, then states 'All experiments in this paper satisfy this condition, so C_total = C_base'; Appendix A.1 repeats that 'cost-mapped routing is disabled.' Consequently the mapping weights W_MAP_DEPTH, W_MAP_CX, W_MAP_SWAP in Table 1 and Fig. 2 are never used, and the claimed hardware awareness reduces to the base structural cost and the decoherence proxy. The authors should either enable SABRE-based transpilation and include mapped depth/CX/SWAP costs in the acquisition, or clearly state that hardware-aware mapping is a proposed extension not evaluated in this work. As written, contribution (3) is not supported by the experiments.
  3. [§4.7, Fig. 12] The noise robustness study is presented as supporting the robustness of the proposed pipeline, but it is performed on a 5-qubit case (Fig. 12 caption) while the main benchmarking is on 8, 10, and 12 qubits, and no comparison is made to the MLP, greedy, or random baselines under the same noise. Reporting that the learned circuits retain accuracy under noise is not sufficient to attribute robustness to the GNN-based search. Moreover, the result that amplitude damping and thermal relaxation improve accuracy by 2–3.5 percentage points over the no-noise baseline is surprising and needs explanation and error bars, as it could stem from a particular circuit/training run rather than a general effect. Without baseline comparisons under identical noise, the robustness claim is not yet established.
minor comments (5)
  1. [Algorithm 1 and §A.2] Algorithm 1 initializes S_0 as empty, while Sec. 4.1 and Appendix A.2 describe warm-starting the surrogate on an initial 50 evaluated circuits. This inconsistency should be clarified.
  2. [Fig. 6] The convergence plots show only 30 iterations on the horizontal axis, while Table 1 says BO_ITERS=100. State whether the plots are truncated or the budget was changed for these runs.
  3. [References] References [17] and [18] are the same paper; one should be removed or replaced with the correct source.
  4. [Fig. 11 caption] The caption states 'The cost-aware BO+VQC+GNN yields systematically lower mapped costs than flat-feature or random baselines,' but the figure shows total gates, CZ count, and depth, not mapped costs. Also, the fixed-budget baselines trivially have the same gate counts by design. Revise the caption to avoid conflating raw complexity with mapped cost.
  5. [Sec. 4.2] The text refers to 'acquisition tempering (Sec. 4.3)' but Sec. 4.3 discusses wall-clock and convergence, not tempering; the cross-reference is incorrect.

Circularity Check

0 steps flagged

No significant circularity: the BO-GNN pipeline is a self-contained search loop; the complexity claim is an explicit objective, not a hidden prediction, though the abstract's 'all baselines' wording is not supported by the paper's own Fig. 11.

full rationale

Walking the derivation chain, the central machinery is a standard Bayesian optimization loop: a GIN+MC-dropout surrogate (Eqs. 17-18) is trained on circuits actually evaluated inside the loop, and acquisition (Eqs. 19-20) uses expected improvement tempered by the explicit cost C_base defined in Eq. 21, which includes normalized depth, two-qubit count, CZ count, total gates, and a decoherence proxy. Reporting that this produces lower-complexity circuits than an unpenalized MLP surrogate is not circular: complexity reduction is an explicit term in the objective, not a quantity that the surrogate is fitted to and then re-predicted. The surrogate's accuracy and ranking are measured against held-out validation performance, and the reported final test accuracies come from retraining the best found circuit on train+validation and evaluating once on the fixed test split, so there is no fitted-input-renamed-as-prediction. The paper's own Sec. 4.6 and Fig. 11 show that the Greedy GNN and Random Search baselines were assigned fixed architectures 'to remove circuit size as a confounding factor', so their gate counts coincide by design; the abstract's claim that the GNN optimizer finds lower complexity 'compared to all baselines' conflicts with those data, but that is a correctness/comparability concern, not a circularity: it is not an equation reducing to an input. Load-bearing external results — GIN expressivity [52], MC-dropout as approximate inference [16], SABRE routing [21], and standard BO [4,31] — are external, code-available, or standard results, and the numerous self-citations in the references are background or application papers, not used to justify the central claim or to rule out alternatives. No uniqueness theorem is imported from the authors, no ansatz is smuggled in via a self-citation, and no known empirical pattern is merely renamed. Therefore, no step in the claimed derivation is equivalent to its own input by construction.

Axiom & Free-Parameter Ledger

10 free parameters · 6 axioms · 0 invented entities

The paper postulates no new physical entities, mediators, forces, or conserved quantities; the decoherence proxy D (Eq. 16) is a heuristic cost term, not an entity. The central claim rests on standard surrogate-modeling assumptions: GIN discriminative power, MC-dropout as epistemic uncertainty, the RY angle-encoding preserving task information, and the noise-channel family approximating NISQ behavior. The most consequential hand-set knobs are the acquisition cost weights and the tempering alpha, which partly engineer the 'low complexity' and 'noise robustness' findings.

free parameters (10)
  • cost-tempering weight alpha = 0.5
    Scales the complexity penalty in ACQ (Eq. 20); hand-set in Table 1; directly shapes the reported 'lower complexity' outcome.
  • base cost weights (W_DEPTH, W_2Q, W_TOTAL, W_CZ) = 0.35, 0.35, 0.15, 0.15
    Eq. (21): hand-set weights defining C_base, the complexity term the paper highlights as an advantage.
  • objective penalty lambda (Eq. 23) = not reported ('small value')
    Regularizes the BO objective perf = acc_val - lambda*penalty; value never given.
  • depolarizing probabilities p_1q, p_2q = not reported
    Applied after each gate in depolarizing mode (Eq. 14); described as constants but numerical values are absent.
  • readout bit-flip probability p_ro = 0.02
    Applied before measurement (Eq. 15); fixed value used in the noise study.
  • mutation probabilities (rho, eta) and max_mutations = 0.10, 0.10, 10
    Define the proposal kernel (Eq. 24); user-set exploration controls in Table 1.
  • feature/qubit count K_FEAT = 7, 8, 9, 10 (per configuration)
    ANOVA-F top-K selection (Sec. 3.1) with K set equal to the qubit count.
  • surrogate hyperparameters (hidden=128, dropout=0.3, MC_SAMPLES=30) = 128 / 0.3 / 30
    GIN architecture and MC-dropout passes (Eq. 18); user-set and directly determine calibration behavior that is never reported.
  • gate times t_1Q = t_2Q = 300 ns
    Converted into noise probabilities (Eq. 10) and the decoherence proxy (Eq. 16).
  • T1/T2 sweep grid = T1 in {20,50,100,200,300,400} us, T2 in {30,60,120,240,360,480} us
    Defines the robustness landscapes in Fig. 13.
axioms (6)
  • standard math GIN achieves WL-test-level graph discrimination and this discriminative power transfers to predicting circuit performance
    Invoked in Secs. 2.3 and 3.3 to justify the surrogate choice; the discrimination bound is a cited result [52], but the transfer from isomorphism discrimination to performance prediction is assumed.
  • domain assumption MC-dropout with 30 stochastic forward passes approximates calibrated epistemic uncertainty
    Eq. (18), the basis of the EI acquisition (Eq. 19). The approximation quality is never verified: calibration metrics defined in App. A.2 (UCE, coverage, NLL) are not reported in the results.
  • domain assumption RY angle-embedding of min-max-scaled features preserves enough information for the binary classification task
    Data encoding choice in Sec. 3.1 (Eqs. 1-4); no ablation against other encodings.
  • domain assumption The AD/PD/GAD/depolarizing/readout channels with gate-time-derived probabilities model NISQ device behavior adequately
    Noise model in Sec. 3.2 (Eqs. 9-15); also the basis for the surprising claim that noise improves accuracy (Fig. 12).
  • domain assumption Local Pauli-Z expectations fed to a two-layer classical MLP form a capable classifier for this data
    Hybrid model in Sec. 3.1 (Eqs. 6-8); no comparison against alternative measurement or readout schemes.
  • domain assumption Validation accuracy during BO transfers to the single final test pass
    Selection rule in Sec. 3.6 and Algorithm 1; the final model is retrained on train+val and evaluated once on test.

reviewed 2026-08-03 · how reviews work

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Cite this review

Pith. "Pith review of Graph-Based Bayesian Optimization for Quantum Circuit Architecture Search with Uncertainty Calibrated Surrogates." pith.science (2026). https://pith.science/paper/KGP47NWQ

@misc{pith2026251209586,
  author       = {Pith},
  title        = {Pith review of: Graph-Based Bayesian Optimization for Quantum Circuit Architecture Search with Uncertainty Calibrated Surrogates},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/KGP47NWQ}},
  note         = {Machine review of arXiv:2512.09586}
}
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read the original abstract

Quantum circuit design is a key bottleneck for practical quantum machine learning on complex, real-world data. We present an automated framework that discovers and refines variational quantum circuits (VQCs) using graph-based Bayesian optimization with a graph neural network (GNN) surrogate. Circuits are represented as graphs and mutated and selected via an expected improvement acquisition function informed by surrogate uncertainty with Monte Carlo dropout. Candidate circuits are evaluated with a hybrid quantum-classical variational classifier on the next generation firewall telemetry and network internet of things (NF-ToN-IoT-V2) cybersecurity dataset, after feature selection and scaling for quantum embedding. We benchmark our pipeline against an MLP-based surrogate, random search, and greedy GNN selection. The GNN-guided optimizer consistently finds circuits with lower complexity and competitive or superior classification accuracy compared to all baselines. Robustness is assessed via a noise study across standard quantum noise channels, including amplitude damping, phase damping, thermal relaxation, depolarizing, and readout bit flip noise. The implementation is fully reproducible, with time benchmarking and export of best found circuits, providing a scalable and interpretable route to automated quantum circuit discovery.

Figures

Figures reproduced from arXiv: 2512.09586 by Muhammad Shafique, Nouhaila Innan, Prashant Kumar Choudhary, Rajeev Singh.

Figure 1
Figure 1. Figure 1: Comparison of two quantum circuits with their feature vectors and graph representations. While aggregate scalar features (e.g., gate counts, depth) can [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Overview of the hardware-aware, graph-based BO pipeline for VQC circuit [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Graph encoding of a quantum circuit. Each node represents a gate [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Best-found 5-qubit architecture returned by BO+VQC+GNN. The circuit exhibits alternating single-qubit rotations (e.g., 𝑅𝑋 , 𝑅𝑌 , 𝑅𝑍 , 𝐻) and selective two-qubit entanglers (e.g., RZZ/CZ/CX depending on the discovered pattern), forming a shallow, cost-efficient design. Reported costs: total gates = [108], CZ gates = [34], depth = [53]. This matches the frontier region where accuracy gains persist while addi… view at source ↗
Figure 5
Figure 5. Figure 5: Wall-time comparison of BO loops. Total BO loop time for [PITH_FULL_IMAGE:figures/full_fig_p010_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Convergence of best-so-far validation accuracy under varying mutation rates. For Mutation 5 (left), both GNN- and MLP-based surrogates rapidly improve [PITH_FULL_IMAGE:figures/full_fig_p011_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Residual convergence behavior of the GIN surrogate across 8-, 10-, and 12-qubit configurations. Each plot shows the evolution of regression residuals over [PITH_FULL_IMAGE:figures/full_fig_p011_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Evolution of surrogate rank fidelity (Kendall– [PITH_FULL_IMAGE:figures/full_fig_p012_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Pareto frontiers of performance versus circuit cost. Non-dominated [PITH_FULL_IMAGE:figures/full_fig_p012_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Accuracy–complexity trade-off across evaluated circuits. Scatter plots show validation accuracy versus total gate count for 8-, 10-, and 12-qubit [PITH_FULL_IMAGE:figures/full_fig_p013_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Complexity metric comparison under acquisition tempering. [PITH_FULL_IMAGE:figures/full_fig_p013_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Noise comparison across quantum noise channels (5-qubit case, [PITH_FULL_IMAGE:figures/full_fig_p014_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Noise robustness via coherence-time sweeps. Validation accuracy landscapes for phase damping, thermal relaxation, and amplitude damping across [PITH_FULL_IMAGE:figures/full_fig_p014_13.png] view at source ↗

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This paper was first reviewed by deepseek-v4-flash on August 3, 2026.