Pith. sign in

REVIEW 9 cited by

BetterV: Controlled Verilog Generation with Discriminative Guidance

Not yet reviewed by Pith; the record is open.

Re-run · record.json Download PDF Read on arXiv ↗

This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.

SPECIMEN: schema-true, not a live event

T0 review · schema-true

One-sentence machine reading of the paper's core claim.

pith:XXXXXXXX · record.json · timestamp

arxiv 2402.03375 v3 pith:NV4TOA5S submitted 2024-02-03 cs.AI cs.PL

Zehua Pei , Hui-Ling Zhen , Mingxuan Yuan , Yu Huang , Bei Yu This is my paper
classification cs.AIcs.PL
keywords verilogdesignbettervgenerationgenerativeguidancellmsdiscriminator
verification ladder T0 review T1 audit T2 compute T3 formal
0 comments
read the original abstract

Due to the growing complexity of modern Integrated Circuits (ICs), there is a need for automated circuit design methods. Recent years have seen rising research in hardware design language generation to facilitate the design process. In this work, we propose a Verilog generation framework, BetterV, which fine-tunes the large language models (LLMs) on processed domain-specific datasets and incorporates generative discriminators for guidance on particular design demands. The Verilog modules are collected, filtered and processed from internet to form a clean and abundant dataset. Instruct-tuning methods are specially designed to fine-tune the LLMs to understand the knowledge about Verilog. Furthermore, data are augmented to enrich the training set and also used to train a generative discriminator on particular downstream task, which leads a guidance for the LLMs to optimize the Verilog implementation. BetterV has the ability to generate syntactically and functionally correct Verilog, which can outperform GPT-4 on the VerilogEval benchmark. With the help of task-specific generative discriminator, BetterV can achieve remarkable improvement on various electronic design automation (EDA) downstream tasks, including the netlist node reduction for synthesis and verification runtime reduction with Boolean Satisfiability (SAT) solving.

Discussion (0). Sign in to comment.

Forward citations

Cited by 9 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code

    cs.AR 2025-09 conditional novelty 6.0 of 10

    AutoVeriFix improves LLM-generated Verilog functional correctness by generating a high-level Python reference model, deriving a high-coverage testbench, and iteratively fixing Verilog simulation mismatches.

  2. Principle-Guided Verilog Optimization: IP-Safe Knowledge Transfer via Local-Cloud Collaboration

    cs.CR 2025-08 conditional novelty 6.0 of 10

    A local-cloud LLM framework improves Verilog power and timing optimization success rates by sending only abstracted design principles to the cloud, not the proprietary RTL code.

  3. RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

    cs.LG 2025-07 conditional novelty 6.0 of 10

    RealBench measures LLM Verilog generation on complex open-source IP cores with formal verification, and all tested models score near zero on full system designs.

  4. ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation

    cs.AR 2025-06 conditional novelty 6.0 of 10

    A reasoning LLM fine-tuned on 3.5B tokens of RTL chain-of-thought data, with iterative test-time self-correction, sets new state-of-the-art results on VerilogEval and RTLLM.

  5. ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation

    cs.AR 2026-07 conditional novelty 5.0 of 10

    On 64 large OpenCores-derived Verilog tasks, top LLMs reach 23.6% functional pass@1, 37.5% pass@5, and 0% on designs with two or more submodules, showing hierarchical RTL generation remains unsolved.

  6. VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs

    cs.SE 2025-07 conditional novelty 5.0 of 10

    A multi-role LLM prompting framework with PPA-aware in-context learning reports 25/29 functional correctness on RTLLM and up to 88% power, 76% area, and 73% timing gains over its own baseline.

  7. DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs

    cs.PL 2025-07 conditional novelty 5.0 of 10

    DecoRTL combines token-class-aware temperature adjustment with contrastive top-K reranking to improve synthesizability and functional correctness of LLM-generated Verilog.

  8. VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation

    cs.AR 2025-07 conditional novelty 4.0 of 10

    A new pipeline and dataset of 20,392 synthesis-checked Verilog modules for LLM fine-tuning is presented, claimed to be the largest high-quality dataset of its kind.

  9. QiMeng: Fully Automated Hardware and Software Design for Processor Chip

    cs.AR 2025-06 conditional novelty 4.0 of 10

    QiMeng is a proposed three-layer architecture for automating processor hardware and software design, with several published components but no integrated implementation yet.

Pith tools