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arxiv: 1907.06069 · v1 · pith:PLCWJRFZnew · submitted 2019-07-13 · ❄️ cond-mat.supr-con · cond-mat.other

Modeling the computer memory based on the ferromagnet/superconductor multilayers

Serhii E. Shafraniuk , Ivan P. Nevirkovets , Oleg A. Mukhanov This is my paper

Pith reviewed 2026-05-24 22:00 UTC · model grok-4.3

classification ❄️ cond-mat.supr-con cond-mat.other
keywords superconducting memorypseudospin valveJosephson transistororthogonal spin transferferromagnet-superconductor multilayermemory cellultrafast switchinglow-energy operation
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The pith

Hybrid pseudospin valve and superconducting-ferromagnetic transistor cells switch in under one nanosecond while using under 100 femtojoules per operation.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper builds a circuit model of memory cells that pair a pseudospin valve with a three-terminal Josephson superconducting-ferromagnetic transistor. Logical 0 and 1 states are stored as two distinct resistance values in the valve; a word pulse on the transistor coincides with a bit pulse on the cell to drive the transistor resistive and flip the valve state. Simulations of individual cells and of circuits containing twelve or thirty cells show that the switching completes in sub-nanosecond times and consumes sub-100 femtojoules. The cells are made from ordinary transition metals and therefore present low impedances between 1 and 30 ohms, allowing direct integration with other superconducting logic. The same model can incorporate noise, crosstalk, and parasitic effects to test larger arrays.

Core claim

The model shows that memory cells built from hybrid pseudospin-valve and superconducting-ferromagnetic-transistor structures achieve ultrafast switching in sub-nanoseconds and energy consumption below 100 femtojoules per operation. Logical states are encoded in the two resistance levels of the pseudospin valve; these levels are toggled when a word pulse applied to the transistor coincides with a bit pulse on the cell, driving the transistor into its resistive state and thereby triggering orthogonal spin transfer inside the valve. The entire dynamics rests on the non-equilibrium and nonstationary properties of the two constituent devices.

What carries the argument

The PS/SFT memory cell circuit in which a three-terminal Josephson superconducting-ferromagnetic transistor controls orthogonal spin transfer inside a pseudospin valve to switch it between two resistance-defined logical states.

If this is right

  • Circuits containing twelve or thirty cells exhibit the same sub-nanosecond switching and sub-100 femtojoule energy figures.
  • The model framework permits direct inclusion of noise, punch-through, crosstalk, and parasitic effects.
  • The cells maintain impedances of 1-30 ohms and therefore integrate with existing superconducting circuits without additional matching networks.
  • Read and write operations are realized by the temporal coincidence of a word pulse on the transistor and a bit pulse on the cell.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Arrays larger than thirty cells could be simulated to locate the onset of thermal or fabrication-induced errors that the present model leaves unexamined.
  • The same non-equilibrium dynamics might be reused to design hybrid magnetic-superconducting logic gates whose switching also relies on controlled spin transfer.
  • Direct connection to Josephson-junction processors would remove the need for separate memory buses and their associated latency.
  • Fabrication tolerances on the thicknesses of the ferromagnetic and superconducting layers could be tested numerically before committing to lithography runs.

Load-bearing premise

The pseudospin valve switches reliably between its two logical resistance states whenever the superconducting-ferromagnetic transistor is driven into its resistive state by overlapping word and bit pulses.

What would settle it

Measure the time and energy required for resistance to change in a fabricated single cell when word and bit pulses are applied simultaneously versus when they are applied separately.

Figures

Figures reproduced from arXiv: 1907.06069 by Ivan P. Nevirkovets, Oleg A. Mukhanov, Serhii E. Shafraniuk.

Figure 1
Figure 1. Figure 1: Computer memory cell (MC) based on the pseudospin [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Non-stationary properties of SFT. (a) The washboard potential U   that tilts stronger as the bias current increases from /0 c II  up to /1 c II  . In SFT, one changes tilt either by adjusting I or c I achieving much better flexibility of control, as compared to a conventional Josephson junction, where the tilt is controlled only by I . (b) The time dependence of the JJ voltage V   , where J  t i… view at source ↗
Figure 4
Figure 4. Figure 4: Experimental data used to building simplified phenomenological models the PS valve 5 . (a) The PS valve, where the out-of-plane polarizer (OP) controls magnetization of the free layer (FL) coupled to the in-plane magnetized reference layer (EB-RL). (b) The OST switching diagram 5-8 modeled by the equation-defined device EDD, according to Eqs. (18)-(21). (c) Switching probability diagram 5 versus voltage VG… view at source ↗
Figure 5
Figure 5. Figure 5: Transition analyzes diagrams of the test circuit (see Figs. A1, A2) of SFT serving as the [PITH_FULL_IMAGE:figures/full_fig_p010_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Model form of the OST switching diagram used in the equation-defined device (EDD). The PS differential resistance dV/dIdc (in ) switches step-wise at Idc=-2 mA and Idc=2.4 mA. The area of the switching loop depends on the pulse duration tpulse, whose optimal value is ~5 ns. changing the injector current. From this [PITH_FULL_IMAGE:figures/full_fig_p012_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Transient simulation results for the PS/SFT cell shown in Fig. A3. [PITH_FULL_IMAGE:figures/full_fig_p013_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Example of the transient simulation the OST [PITH_FULL_IMAGE:figures/full_fig_p014_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: S-parameter simulation results for the memory cell shown in Fig.8 [PITH_FULL_IMAGE:figures/full_fig_p016_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: The transient analyzes diagrams reflecting the time [PITH_FULL_IMAGE:figures/full_fig_p017_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: The bit-error rate (BER) of the memory circuit for reading/writing at  = 1 GHz (blue, red) and  = 1.5 GHz (cyan, yellow) obtained in the course of the multiple simulation cycles with changing the initial conditions that resulted in a variety of error events [PITH_FULL_IMAGE:figures/full_fig_p019_11.png] view at source ↗
read the original abstract

A model of superconducting computer memory exploiting the orthogonal spin transfer (OST) in the pseudospin valve (PS) that is controlled by the three-terminal Josephson superconducting-ferromagnetic transistor (SFT) is developed. The building blocks of the memory are hybrid PS and SFT structures. The memory model is formulated in terms of the equation-defined PS and SFT devices integrated into the PS/SFT memory cell (MC) circuit. Logical units "0" and "1" are associated with the two PS states respectively characterized by two different values of resistance. Elementary logical operations comprising the read/write processes occur when a word pulse applied to the SFT's injector coincides with the respective bit pulse acting on MC. Physically, a word pulse triggers SFT to a resistive state, causing the PS switching between the logical "0" and "1" states. Thus, the whole switching dynamics of MC depends on the non-equilibrium and nonstationary properties of PS and SFT. Modeling the single MC as well as the larger MC-based circuits comprising respectively twelve and thirty elements suggest that such the memory cells can undergo ultrafast switching (sub-ns) and low energy consumption per operation (sub-100 fJ). The suggested model allows studying the influence of noises, punch-through effect, crosstalk, parasitic, etc. The obtained results suggest that the hybrid PS/SFT structures are well-suited to superconducting computing circuits as they are built of magnetic and non-magnetic transition metals and therefore have low impedances (1-30 Ohm).

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript develops a phenomenological model for a superconducting memory cell (MC) that combines a pseudospin valve (PS) whose two resistance states encode logical 0/1 with a three-terminal Josephson superconducting-ferromagnetic transistor (SFT) that controls switching via coincident word and bit pulses. The model is expressed as equation-defined PS and SFT blocks integrated into single-MC and multi-element (12- and 30-element) circuits; read/write operations are asserted to occur when an SFT is driven resistive, thereby driving the PS between its two states. Simulations of the resulting non-equilibrium, nonstationary dynamics are reported to yield sub-ns switching times and sub-100 fJ energy per operation, with the structures noted for their low (1-30 Ω) impedances.

Significance. If the underlying rate equations and critical-current densities prove to be realistic, the hybrid PS/SFT approach could supply a low-impedance, magnetically controlled element compatible with superconducting logic. The explicit construction of larger MC arrays and the stated ability to incorporate noise, punch-through, and crosstalk are methodological strengths that would allow systematic exploration of scalability.

major comments (2)
  1. [Abstract] Abstract (and modeling-results paragraphs): the quantitative claims of sub-ns switching and sub-100 fJ energy per operation are presented as direct outputs of the PS/SFT circuit simulations, yet no calibration of the model equations or parameters against measured I-V curves, switching times, or energy scales of comparable PS or SFT devices is reported. Because the logical switching step rests entirely on the non-equilibrium dynamics of the two blocks, the absence of such anchoring makes the reported performance figures sensitive to arbitrary choices in the rate equations and critical-current densities.
  2. [Model formulation] Model-formulation section: the switching assertion that “a word pulse triggers SFT to a resistive state, causing the PS switching between the logical ‘0’ and ‘1’ states” is stated without an explicit derivation or reference to the coupled differential equations that govern the joint nonstationary evolution of the two devices. Consequently it is impossible to judge whether the sub-ns / sub-100 fJ figures are robust predictions or artifacts of the particular phenomenological closure chosen for the PS and SFT blocks.
minor comments (2)
  1. Grammatical phrasing: “such the memory cells”, “the whole switching dynamics of MC depends”, and “comprising respectively twelve and thirty elements” should be corrected for clarity.
  2. [Abstract] The abstract states that the model “allows studying the influence of noises, punch-through effect, crosstalk, parasitic, etc.” but does not indicate whether these effects were actually included in the reported 12- and 30-element simulations.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the careful reading and constructive comments. We address each major comment below, indicating where the manuscript will be revised to strengthen the presentation of the model and its results.

read point-by-point responses

  1. Referee: [Abstract] Abstract (and modeling-results paragraphs): the quantitative claims of sub-ns switching and sub-100 fJ energy per operation are presented as direct outputs of the PS/SFT circuit simulations, yet no calibration of the model equations or parameters against measured I-V curves, switching times, or energy scales of comparable PS or SFT devices is reported. Because the logical switching step rests entirely on the non-equilibrium dynamics of the two blocks, the absence of such anchoring makes the reported performance figures sensitive to arbitrary choices in the rate equations and critical-current densities.

    Authors: We agree that the manuscript would be improved by explicit discussion of parameter selection. The rate equations and critical-current densities are phenomenological and drawn from typical values reported for PS and SFT structures in the literature. In the revised version we will add a dedicated subsection (or table) listing the parameter sources, ranges, and a short sensitivity study showing that the sub-ns and sub-100 fJ scales remain within the stated bounds for plausible variations. revision: yes

  2. Referee: [Model formulation] Model-formulation section: the switching assertion that “a word pulse triggers SFT to a resistive state, causing the PS switching between the logical ‘0’ and ‘1’ states” is stated without an explicit derivation or reference to the coupled differential equations that govern the joint nonstationary evolution of the two devices. Consequently it is impossible to judge whether the sub-ns / sub-100 fJ figures are robust predictions or artifacts of the particular phenomenological closure chosen for the PS and SFT blocks.

    Authors: The PS and SFT blocks are implemented as equation-defined devices whose individual dynamics are integrated within the circuit simulator. We acknowledge that an explicit statement of the coupled equations describing the joint non-stationary evolution would make the switching mechanism clearer. The revised manuscript will include a short subsection that writes out (or references) the coupled differential equations used for the combined PS/SFT cell. revision: yes

Circularity Check

0 steps flagged

No significant circularity in derivation chain

full rationale

The paper formulates a model using equation-defined PS and SFT blocks, integrates them into MC circuits, and reports simulation outputs for sub-ns switching and sub-100 fJ energy. These metrics are direct results of running the described non-equilibrium dynamics under coincident pulses rather than any reduction to fitted parameters, self-defined quantities, or self-citation chains. No load-bearing step equates a claimed prediction to its own inputs by construction; the work is a self-contained modeling study whose quantitative outputs depend on the chosen rate equations but are not forced by definition or prior self-citation.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Only abstract available; cannot identify specific free parameters, axioms, or invented entities from provided text.

pith-pipeline@v0.9.0 · 5822 in / 926 out tokens · 26704 ms · 2026-05-24T22:00:53.071442+00:00 · methodology

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Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

  • IndisputableMonolith/Cost/FunctionalEquation.lean washburn_uniqueness_aczel unclear
    ?
    unclear

    Relation between the paper passage and the cited Recognition theorem.

    The memory model is formulated in terms of the equation-defined PS and SFT devices integrated into the PS/SFT memory cell (MC) circuit... the whole switching dynamics of MC depends on the non-equilibrium and nonstationary properties of PS and SFT.

  • IndisputableMonolith/Foundation/RealityFromDistinction.lean reality_from_one_distinction unclear
    ?
    unclear

    Relation between the paper passage and the cited Recognition theorem.

    Modeling the single MC as well as the larger MC-based circuits comprising respectively twelve and thirty elements suggest that such the memory cells can undergo ultrafast switching (sub-ns) and low energy consumption per operation (sub-100 fJ).

What do these tags mean?
matches
The paper's claim is directly supported by a theorem in the formal canon.
supports
The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends
The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses
The paper appears to rely on the theorem as machinery.
contradicts
The paper's claim conflicts with a theorem or certificate in the canon.
unclear
Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

Works this paper leans on

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    Introduction Issues of the local overheating and thermal management in the contemporary digital semiconducting circuits, serving as an element base for nowadays computers, represent the major impediment to the progress in this area 9. Presently, computing information is processed by transmitting the electric pulses that trigger logic elements in a circuit...

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