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REVIEW 3 major objections 5 minor 25 references

Cloud LLMs can size real analog circuits without ever seeing foundry PDK content, proprietary schematics, or simulator paths.

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2026-07-12 00:33 UTC pith:R5HOO5FD

load-bearing objection Real NDA-safe Virtuoso/Maestro loop with honest multi-model PVT evidence; the architecture is the durable piece, the 4/11 op-amp pass is a thin existence claim. the 3 major comments →

arxiv 2607.03701 v1 pith:R5HOO5FD submitted 2026-07-04 cs.AR cs.CRcs.LG

SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows

Xunqi Li , Chris H. Kim This is my paper
classification cs.AR cs.CRcs.LG
keywords LLM agentsanalog circuit optimizationEDA automationCadence VirtuosoMaestroSpectreNDA-safe design automationLLM4EDA
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Industrial analog design cannot simply hand a foundry process design kit, private schematic hierarchy, absolute host paths, or license-bound tool state to a cloud language model. This paper shows that a carefully engineered tool boundary is enough to let those models still run closed-loop optimization through commercial Cadence Virtuoso, Maestro, and Spectre. The framework returns only scrubbed topology intent, numeric metrics, a short whitelist of operating-point scalars, and write-back status, under an explicit curious-but-passive cloud-provider threat model. From the same documented all-ones reset, eleven model checkpoints are scored on two process–voltage–temperature tasks that gate every hard metric on the worst of three corners: a 20 GHz LC-VCO tuning-curve task and a two-stage op-amp task whose phase-margin gate rejects unstable high-gain points. Seven of eleven models close the VCO loop and four close the harder op-amp loop inside a fifteen-iteration budget. Removing any one sanitized feedback channel either silently drops part of the specification or measurably weakens the search, showing that the boundary itself is load-bearing rather than decorative. The practical claim is therefore that cloud models can be used and fairly compared inside real foundry-bound analog flows, provided reliability is judged at the level of the complete tool loop—contract discipline, endpoint stability, and metric-driven repair—rather than free-form text reasoning alone.

Core claim

An NDA-safe closed-loop boundary—whitelist of 28 scoped SKILL entry points, return-path scrubbing, strict JSON action contract, Maestro write-back with landing verification, and best-so-far state preservation—still supplies enough sanitized evidence for cloud LLMs to optimize real analog circuits under three-corner PVT sign-off, with 7 of 11 models passing an LC-VCO task and 4 of 11 passing a harder phase-margin-gated op-amp task from an identical reset.

What carries the argument

SABLE: a SafeBridge that confines the model to 28 whitelisted SKILL entry points, scrubs every return path of PDK tokens and absolute paths, enforces a strict JSON design-variable contract with six machine-checked stop conditions, and returns only anonymized topology intent, worst-corner metrics, and a 20-key operating-point table.

Load-bearing premise

The cloud provider is only a curious passive observer of prompts and tool results; it does not actively compromise the local host, and provider-side retention or aggregate inference of device-model parameters from the scrubbed operating-point scalars is treated as out of scope.

What would settle it

A red-team extraction or multi-seed ablation in which a protected PDK token, absolute path, or model-card quantity reaches the model, or in which removing the scrubbed channels still leaves every model unable to close either PVT task from the same reset, would falsify the central claim.

Watch this falsifier — get emailed when new claim-graph text bears on it.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. SABLE is an NDA-safe closed-loop framework that lets cloud LLMs size analog circuits through Cadence Virtuoso/Maestro/Spectre while returning only scrubbed topology intent, numeric metrics, operating-point summaries, and writeback status. The paper contributes an explicit curious-but-passive threat model with a four-tier attack ladder and five hard invariants; a whitelist of 28 SKILL entry points; return-path PDK/path scrubbing; a strict JSON action contract with six machine-checked stop conditions; Maestro setup/writeback with landing verification; and a fair-start benchmark protocol. Eleven LLM checkpoints are evaluated from a documented all-ones reset on two proprietary 16 nm FinFET tasks under the same three-corner PVT worst-corner gate: a 20 GHz LC-VCO tuning-curve task (7/11 pass) and a two-stage op-amp task with a phase-margin stability gate (4/11 pass). Single-checkpoint feedback-path ablations and a terminal-cause taxonomy support the claim that sanitized channels are load-bearing and that model quality differs sharply once tool discipline and bias/stability reasoning are required.

Significance. If the result holds, this is a practically important systems contribution for industrial analog EDA: it shows how to put a licensed Virtuoso/Maestro/Spectre flow behind an enforced model-provider trust boundary rather than assuming open PDKs or on-premise models. Strengths that should be credited include the explicit threat model and attack ladder (Table 2), structural allowlists versus best-effort scrubbing, authoritative recomputation of measurements so models cannot talk their way into a pass, logged terminal causes that make the failure taxonomy quantitative, the public reproducibility package with leak-check scripts and 0% ASR under fixed/live/adaptive probes (Table 11), and the fair-start protocol that makes multi-model comparison meaningful. The work is complementary to prior analog LLM sizing systems (Table 1) precisely because none of them enforce a cloud-provider boundary on a real Cadence ADE flow.

major comments (3)
  1. [Section 6, Tables 7–8; Section 10] Tables 7–8 and Section 6 rest the multi-model and “enough sanitized feedback” claims on a single audited seed-1 run per model with a 15-iteration budget. Section 10 and the Section 7 ablation note already concede that budget and endpoint state can flip individual outcomes; with only 4/11 op-amp passes, loss of one or two of those rows would leave the harder-task half of the central existence claim without demonstrated success under the same fair-start protocol. Multi-seed replication (or at least a second seed on the four op-amp passers and the near-miss unstable points) is load-bearing for the published pass-rate claims, not merely a nice-to-have extension.
  2. [Section 7, Table 9] Section 7’s feedback-path ablations are design-motivating case observations on a single mid-tier checkpoint (mimo-v2.5-pro), single seed, 5-iteration budget, and the single-corner base LC-VCO variant (including a different Kvco ceiling). The main empirical claim is three-corner PVT with worst-corner gating. Because the paper uses these ablations to argue that individual sanitized channels are load-bearing for successful optimization, the ablation setting should match the main PVT protocol (or the mismatch should be closed with at least one PVT ablation of the swept-metric and curve-searcher channels).
  3. [Section 5.1 (Two-stage op-amp PVT)] Section 5.1 states that the two most extreme corners of a five-corner set were excluded after exploratory runs showed no sizing point held gain at slow/cold/0.72 V, so those corners would make the op-amp task unsatisfiable by construction. That pruning is reasonable for discriminability, but the paper repeatedly frames both tasks as “PVT sign-off” under a shared envelope. The manuscript should more clearly bound what “PVT” means here (a feasible three-corner subset, not a full foundry sign-off suite) and report, even briefly, the exploratory evidence that justified dropping the two corners, so readers can judge whether the 4/11 pass rate reflects a realistic industrial gate or a post-selected feasible envelope.
minor comments (5)
  1. [Table 1] Table 1’s “Real Cad.” column for AMSnet-KG is annotated as batch Spectre without Virtuoso/Maestro ADE; consider making that distinction in the table body rather than only in the footnote so the positioning claim is self-contained.
  2. [Figure 5] Figure 5 shows only passing LC-VCO Kvco curves; a short note in the caption that failing runs never reached the sweep phase (already in the table footnote) would make the figure self-explanatory.
  3. [Table 6; Section 4.2] The op-amp design-variable table (Table 6) declares no per-variable ranges, unlike Table 4 for the LC-VCO. A sentence on how physical-plausibility bounds are enforced at the bridge would help readers interpret search coverage.
  4. [Section 5.2; Section 10] Several model names (e.g., claude-opus-4-8, gpt-5.5, minimax-m3) are dated endpoint snapshots; stating the access window or API date in Section 5.2 or the artifact README would strengthen the “dated snapshot” disclaimer in Section 10.
  5. [Abstract; Section 1] Minor consistency: abstract says “propose circuit-optimization decisions” while the introduction opens with “circuit-sizing decisions”; aligning terminology would avoid implying topology synthesis.

Circularity Check

0 steps flagged

No circular derivation: empirical closed-loop evaluation against an independent Spectre oracle and fixed metric bands, not a first-principles prediction forced by its inputs.

full rationale

SABLE is a systems/engineering paper whose central claims are (i) an enforceable NDA-safe tool boundary under a stated threat model and (ii) empirical existence of successful closed-loop PVT optimization under that boundary (7/11 LC-VCO, 4/11 op-amp). Pass/fail is recomputed authoritatively on the trusted side from Spectre/Maestro results against fixed, machine-readable bands (Tables 3 and 5); the model’s own measurements field cannot talk a run into a pass. No free parameter is fitted to a data subset and then re-presented as a prediction of a closely related quantity. The optional deterministic curve-searcher is ablated (Table 9) and shown not to force success. The three-corner PVT envelope is a deliberate, disclosed feasibility choice after exploratory five-corner runs, not a self-definitional reduction of a derived claim to its inputs. There are no load-bearing self-citations, uniqueness theorems imported from the authors, or ansatzes smuggled via prior work by the same authors. Residual definitional scoping (“NDA-safe” means enforcement under the stated curious-but-passive model, not non-interference) is explicit and does not make the optimization results circular. Statistical fragility of single-seed pass rates is a correctness/support concern, not circularity.

Axiom & Free-Parameter Ledger

5 free parameters · 4 axioms · 4 invented entities

The central claim is an engineering existence result plus empirical multi-model outcomes. It rests on a stated adversary model, structural allowlists, a pattern scrubber, fixed task hyperparameters (budget, corners, pass bands), and the SABLE components themselves. No physical constants are fitted; free parameters are protocol knobs that affect ranking stability but not the existence of successful sanitized loops.

free parameters (5)
  • iteration_budget = 15
    Fixed at 15 for the matched tables; Section 7 notes rankings are budget-sensitive (deepseek-v4-flash fails at 5 iters, passes at 15).
  • PVT_corner_set = tt/25C/0.80V, ss/125C/0.72V, ff/-40C/0.88V
    Three corners retained after exploratory five-corner runs excluded two extremes that made the op-amp task unsatisfiable by construction (Section 5.1).
  • hard_pass_bands = task-specific bands in Tables 3 and 5
    Metric thresholds (f_osc [19.5,20.5] GHz, A0>=45 dB, PM>=45 deg, etc.) are design choices calibrated for feasibility under the chosen corners and all-ones reset.
  • OP_whitelist_size = 20 keys
    20 operating-point keys chosen by authors; bounds what bias evidence the model may see.
  • SKILL_entry_point_count = 28
    28 scoped wrappers (25 safe* + 3 aliases) define the structural allowlist.
axioms (4)
  • domain assumption Cloud LLM provider is curious-but-passive: observes prompts and tool results, may log or train, may return adversarial arguments, but does not compromise the local OS or Cadence process and does not mount active MITM on the EDA host.
    Section 3.1; defines the entire NDA-safe claim. Stronger adversaries are out of scope.
  • domain assumption Structural allowlists (design-variable names, 28 SKILL entry points, 20 OP keys) bound what the boundary can emit by construction; content outside the lists is unreachable.
    Section 3.3 invariants 2, 3, 5; primary confidentiality guarantee.
  • ad hoc to paper Pattern-based return-path scrubber plus known-root path allowlist is sufficient defense-in-depth for residual free-text fields under the stated threat model.
    Section 3.3 invariant 1 and Section 9; authors note an unmatched identifier can pass and that foundries must extend the pattern list.
  • domain assumption Worst-corner-must-pass gating across the three retained corners is a valid and discriminating industrial sign-off for the two tasks.
    Sections 5.1 and 6; standard analog practice, but the corner set itself was pruned after exploration.
invented entities (4)
  • SABLE / SafeBridge NDA-safe closed-loop architecture no independent evidence
    purpose: Wrap Cadence SKILL/OCEAN so cloud LLMs can optimize analog circuits without receiving PDK, paths, or raw simulator state.
    Core contribution; no independent existence outside this paper.
  • Strict JSON action contract with six machine-checked stop conditions no independent evidence
    purpose: Force tool discipline, enable repair, and produce quantitative terminal-cause taxonomy.
    Section 4.3; protocol invention of the paper.
  • Anonymized topology-intent readback and 20-key operating-point whitelist no independent evidence
    purpose: Supply bias and connectivity evidence without model-card or cell-name leakage.
    Section 4.5; residual aggregate-inference channel acknowledged as out of scope.
  • Deterministic curve-searcher feedback module no independent evidence
    purpose: Optional PDK-safe directional hints for swept tuning-curve metrics.
    Section 4.5/5.1; ablated in Section 7 and shown load-bearing for the base LC-VCO variant.

pith-pipeline@v1.1.0-grok45 · 25633 in / 3845 out tokens · 45156 ms · 2026-07-12T00:33:08.521744+00:00 · methodology

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read the original abstract

Large language models (LLMs) can propose circuit-optimization decisions, but industrial analog flows cannot expose foundry PDK content, proprietary schematics, absolute simulation paths, or license-bound tool state to a cloud endpoint. We present SABLE (Safe Analog Boundary for LLM-driven EDA), an NDA-safe closed-loop framework that lets LLMs optimize analog circuits through Cadence Virtuoso, Maestro, and Spectre while returning only scrubbed topology intent, numeric metrics, operating-point summaries, and scoped writeback status. "NDA-safe" denotes enforcement under a stated curious-but-passive cloud-provider threat model, not a formal non-interference proof. The framework combines an explicit threat model, a whitelist of 28 scoped SKILL entry points, PDK/path/model scrubbing on every return path, structured Maestro setup and writeback, a strict JSON action contract with six machine-checked stop conditions, and best-so-far state preservation. We evaluate eleven LLM checkpoints from the same documented reset state on two real closed-loop tasks, both run as process-voltage-temperature (PVT) sign-offs across three corners: a 20 GHz LC-VCO tuning-curve task and a two-stage op-amp task. On the LC-VCO task 7 of 11 models pass; on the harder op-amp task, where every metric must hold at the worst corner and a phase-margin gate rejects unstable high-gain points, 4 of 11 pass within a 15-iteration budget. Feedback-path ablations show that removing individual sanitized channels either silently weakens the specification or degrades the search. Model quality differs sharply once the loop requires tool discipline, bias reasoning, and specification repair, yet an NDA-safe boundary still provides enough sanitized feedback for successful analog circuit optimization.

Figures

Figures reproduced from arXiv: 2607.03701 by Chris H. Kim, Xunqi Li.

Figure 1
Figure 1. Figure 1: Conceptual overview of SABLE. The LLM sees JSON actions and scrubbed observations. Foundry PDK [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: SABLE data flow. The cloud LLM receives JSON actions and scrubbed observations only. PDK content [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: LC-VCO topology: a cross-coupled NMOS pair ( [PITH_FULL_IMAGE:figures/full_fig_p009_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Two-stage Miller-compensated op-amp (single-ended core shown): an NMOS input pair ( [PITH_FULL_IMAGE:figures/full_fig_p011_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Per-segment 𝐾𝑉𝐶𝑂 of each passing model’s final LC-VCO design point over the 𝑉𝑐𝑡𝑟𝑙 sweep at the nominal corner, from the benchmark artifacts. All seven passing models stay inside the [150, 3000] MHz/V per-segment band (dashed/dotted red). The four failing runs are absent because they never cleared the single-point worst-corner 𝑓𝑜𝑠𝑐 gate that precedes the tuning sweep. op-amp PVT loop while missing LC-VCO—so… view at source ↗

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