Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 4 inbound Pith citation observations for arXiv:2304.13840.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-04T20:43:13.097994Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-06-29T18:53:51.308175Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation a42ed1ab-3222-47a1-a07e-ef6f8639baf4 · inbound
AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code cites this paper.
AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
Reference 4
- Resolution
- unresolved
- no resolver link, observed 2026-08-04T20:43:13.097994Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 32acace1-6ab7-4fd9-be51-dd70500f2f90 · inbound
VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation cites this paper.
VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
Reference 7
- Resolution
- verified exact
- arxiv_id, observed 2026-05-11T12:11:06.977926Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.
Observation f5775942-b303-4781-8ce7-3ccc798239c8 · inbound
Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation cites this paper.
Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
Reference 22
- Resolution
- verified exact
- arxiv_id, observed 2026-06-29T18:53:51.310694Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.
Observation 360329f0-ddec-4902-8442-1b74967c8651 · inbound
ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation cites this paper.
ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
Reference 8
- Resolution
- unresolved
- no resolver link, observed 2026-08-02T07:12:16.918016Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.