pith. sign in

arxiv: 2605.07936 · v2 · pith:XRAFR5G3new · submitted 2026-05-08 · 📡 eess.SP

A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology

Arthur Fyon , Loris Mendolia , Jean-Michel Redout\'e , Alessio Franci , Guillaume Drion This is my paper

Pith reviewed 2026-05-20 22:42 UTC · model grok-4.3

classification 📡 eess.SP
keywords current-mode circuitmemory cellSchmitt triggertunable hysteresisneuromorphic computingCMOSlow powerspike-based logic
0
0 comments X

The pith

A nine-transistor current-mode circuit in standard CMOS provides independent tuning of threshold current, hysteresis width, and output gain for bistable memory.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents a memory cell that works entirely with currents rather than voltages. It uses a feedback loop between two simple thresholding circuits to create stable on and off states that can be adjusted separately for when it switches, how wide the switching gap is, and how strong the output is. This design uses only nine transistors and very little power, making it suitable for building logic gates and recurrent units in analog computing systems without needing clocks or refresh cycles. A sympathetic reader would care because it offers a compact, tunable building block for neuromorphic hardware that integrates memory directly into computation.

Core claim

By connecting two interdependent Heaviside-like thresholding elements in a novel feedback configuration, a nine-transistor circuit in standard CMOS produces tunable bistable switching behavior in the current domain, with threshold current, hysteresis width, and output gain set independently by bias currents.

What carries the argument

A novel feedback configuration between two interdependent Heaviside-like thresholding elements that generates tunable bistable switching.

If this is right

  • Spike-based logic gates can be built using three-level current encoding where the memory cell retains the polarity of the last spike indefinitely.
  • The same cell serves as the primitive for Bistable Memory Recurrent Units in analog neural networks with inherent noise immunity from quantized states.
  • The design enables asynchronous logic operations without temporal windowing or refresh mechanisms.
  • Neuromorphic processors can integrate memory, logic, and recurrent computation using this versatile building block.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the tunability holds in silicon, it could simplify the design of large-scale analog computing arrays by reducing the need for additional calibration circuits.
  • The current-domain operation might allow direct interfacing with other current-mode neuromorphic components without voltage conversion overheads.
  • Resilience to device mismatch as shown in simulations suggests potential for reliable operation in mass-produced chips.
  • Extending the family of logic gates could lead to more complex asynchronous state machines in hardware.

Load-bearing premise

The schematic-level simulations in a 180 nm CMOS process accurately predict the behavior of fabricated chips, including stable hysteresis and tunability despite device mismatch and parasitics.

What would settle it

Fabricating the circuit in silicon and measuring that the three parameters cannot be tuned independently or that hysteresis collapses under realistic process variations would disprove the claims.

Figures

Figures reproduced from arXiv: 2605.07936 by Alessio Franci, Arthur Fyon, Guillaume Drion, Jean-Michel Redout\'e, Loris Mendolia.

Figure 1
Figure 1. Figure 1: Conceptual architecture of the proposed dual-Heaviside feedback Schmitt trigger, along with the electronic schematics of the individual Heaviside circuit and the full Schmitt trigger. The hysteresis behavior arises naturally from the feedback current Iwidth, which lowers the effective input threshold to Ithresh − Iwidth, thus enabling bistability. The three control parameters Ithresh, Igain, and Iwidth are… view at source ↗
Figure 2
Figure 2. Figure 2: A. Transient simulation of the proposed Schmitt trigger under triangular input current for different operating temperatures. B. DC sweep demonstrating hysteretic behavior for different operating temperatures. C. Monte Carlo analysis of the proposed Schmitt trigger in DC input sweep analysis with 3σ process variation at room temperature. Baseline parameters: Igain = 486 pA, Ithresh = 368 pA, and Iwidth = 21… view at source ↗
Figure 3
Figure 3. Figure 3: A. Igain DC sweep analysis from 0 to 500 pA of the proposed Schmitt trigger for different operating temperatures. B. Ithresh DC sweep analysis from 100 pA to 400 pA of the proposed Schmitt trigger for different operating temperatures with Iwidth = 50 pA. C. Iwidth DC sweep analysis from 10 pA to 300 pA of the proposed Schmitt trigger for different operating temperatures. Baseline parameters: Igain = 486 pA… view at source ↗
Figure 4
Figure 4. Figure 4: Circuit implementation of the XOR logic gate using the proposed Schmitt trigger. Each input is processed by both a standard and an inverted Schmitt trigger to detect spike polarity. The outputs are summed and thresholded to produce the XOR operation. The other four logic gates (AND, OR, NAND, NOR) follow analogous configurations with different summation and threshold arrangements. For the AND gate, Ist1 an… view at source ↗
Figure 5
Figure 5. Figure 5: Simulation results of all five spike-based logic gates (AND, NAND, OR, NOR, XOR) for different input spike polarity combinations (top). The three-level current encoding (0 pA = logic 0 / negative spike, 250 pA = undefined / no spike received, 500 pA = logic 1 / positive spike) enables bidirectional logic operations while maintaining the unipolar current constraint. Each gate correctly responds to the polar… view at source ↗
read the original abstract

This work introduces a fully tunable, ultra-low power unipolar memory cell inspired by the Schmitt-trigger comparator and designed in CMOS using only nine transistors. The proposed circuit operates entirely in the current domain and exploits a novel feedback configuration between two interdependent Heaviside-like thresholding elements to produce tunable bistable switching behavior. Its three key parameters-threshold current, hysteresis width, and output gain-are independently tunable via programmable bias currents, enabling flexibility across diverse analog computing applications. Unlike prior Schmitt-trigger designs, it simultaneously achieves current-mode operation, nanowatt-range power consumption, temperature stability, and full tunability, solely using standard MOSFET elements. Schematic-level simulations in a 180 nm CMOS process confirm robust hysteresis and resilience to device mismatch. Building on this circuit, we develop a complete family of spike-based logic gates using three-level current encoding, where the bistable memory retains the polarity of the last spike on each input indefinitely, enabling asynchronous logic operations without temporal windowing or refresh mechanisms. The same circuit also serves as the primitive for Bistable Memory Recurrent Units in analog neural networks, where the quantized hidden states provide inherent noise immunity. Together, these capabilities position the design as a versatile building block for next-generation neuromorphic processors integrating memory, logic, and recurrent computation.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper introduces a nine-transistor current-mode memory cell in standard CMOS that uses a novel feedback loop between two interdependent Heaviside-like thresholding elements to realize bistable switching. The design claims independent tunability of threshold current, hysteresis width, and output gain through programmable bias currents, with schematic simulations in 180 nm CMOS demonstrating nanowatt power, temperature stability, mismatch resilience, and applications to spike-based logic gates and bistable memory recurrent units.

Significance. If the reported behavior holds in silicon, the circuit would provide a compact, fully tunable ultra-low-power primitive that integrates memory, logic, and recurrent computation for neuromorphic systems, improving on prior Schmitt-trigger memory cells by achieving current-domain operation and independent parameter control with minimal transistors. The simulation-based verification of robust hysteresis is a positive but limited strength.

major comments (2)
  1. [§III] §III (Simulation Results): The claims of independent control over threshold current, hysteresis width, and output gain, plus mismatch resilience, rest exclusively on schematic-level netlist simulations. No post-layout parasitic extraction or measured silicon data are presented, leaving open whether interconnect capacitances and resistances on the current-mirror and feedback nodes couple the three parameters or shrink the bistable region, directly undermining the central tunability and ultra-low-power assertions.
  2. [§II] §II (Circuit Topology): The novel feedback configuration is asserted to produce truly independent tuning via bias currents alone, yet the manuscript provides no small-signal or large-signal analysis deriving the three parameters as functions of the bias currents; independence is shown only by sweeping bias values in simulation, which is load-bearing for the 'fully tunable' and 'parameter-free' positioning relative to prior work.
minor comments (2)
  1. [Figures] Figure captions and axis labels in the simulation plots should explicitly state whether the curves include or exclude post-layout parasitics.
  2. [Abstract] The abstract states 'temperature stability' without referencing the specific temperature range or simulation conditions used to support this claim.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the constructive review and positive assessment of the circuit's potential impact. We address the two major comments point by point below, proposing specific revisions to strengthen the manuscript while being transparent about current limitations.

read point-by-point responses

  1. Referee: [§III] §III (Simulation Results): The claims of independent control over threshold current, hysteresis width, and output gain, plus mismatch resilience, rest exclusively on schematic-level netlist simulations. No post-layout parasitic extraction or measured silicon data are presented, leaving open whether interconnect capacitances and resistances on the current-mirror and feedback nodes couple the three parameters or shrink the bistable region, directly undermining the central tunability and ultra-low-power assertions.

    Authors: We agree that schematic simulations alone leave open questions about parasitic coupling. In the revised manuscript we will add post-layout simulations with extracted parasitics from a complete layout to verify that independent tunability of the three parameters and the size of the bistable region are preserved. We will also include a short discussion of expected parasitic effects on the current-mirror and feedback nodes. Measured silicon data cannot be provided at this stage because the design has not yet been fabricated; we will explicitly note this limitation and outline plans for future tape-out and measurement. revision: partial

  2. Referee: [§II] §II (Circuit Topology): The novel feedback configuration is asserted to produce truly independent tuning via bias currents alone, yet the manuscript provides no small-signal or large-signal analysis deriving the three parameters as functions of the bias currents; independence is shown only by sweeping bias values in simulation, which is load-bearing for the 'fully tunable' and 'parameter-free' positioning relative to prior work.

    Authors: We accept that an analytical derivation would strengthen the claims. We will add a dedicated subsection in §II that presents a large-signal analysis of the interdependent feedback loop and derives approximate closed-form expressions for threshold current, hysteresis width, and output gain as functions of the three bias currents. These expressions will be cross-validated against the existing simulation sweeps and will clarify the degree of independence relative to earlier Schmitt-trigger memory cells. revision: yes

standing simulated objections not resolved
  • Measured silicon data cannot be supplied because the circuit has only been simulated and has not been fabricated.

Circularity Check

0 steps flagged

No circularity: circuit topology verified by simulation

full rationale

The paper presents a proposed nine-transistor current-mode memory cell topology whose bistable behavior and independent tunability of threshold current, hysteresis width, and output gain are demonstrated via schematic-level simulations in 180 nm CMOS. No algebraic derivations, equations, or first-principles results are claimed that reduce to fitted parameters or self-referential inputs by construction. The design is introduced as a novel feedback configuration between thresholding elements, with performance claims resting on external simulation verification rather than internal fitting loops, self-citation chains, or renamed empirical patterns. This is a standard self-contained circuit design paper whose central claims do not collapse into their own inputs.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The design relies on standard MOSFET models and simulation assumptions rather than new physical postulates; bias currents serve as tunable inputs rather than fitted free parameters.

free parameters (1)
  • programmable bias currents
    Three independent bias currents set threshold, hysteresis width, and output gain; these are design choices rather than data-fitted constants.
axioms (1)
  • domain assumption Standard 180 nm CMOS process models accurately capture device behavior for schematic-level hysteresis analysis
    Invoked when claiming robust hysteresis and mismatch resilience from simulations.

pith-pipeline@v0.9.0 · 5769 in / 1306 out tokens · 28419 ms · 2026-05-20T22:42:44.851471+00:00 · methodology

Review history (2 revisions) →

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

51 extracted references · 51 canonical work pages · 4 internal anchors

  1. [1]

    A current-mode multiply-accumulate macro in sensing-computing fusion system for feature extraction and redundancy reduction

    X. Ren et al. “A current-mode multiply-accumulate macro in sensing-computing fusion system for feature extraction and redundancy reduction”. In:IEEE Trans. Circuits Syst. II, Exp. Briefs(2025).doi:10.1109/tcsii.2025.3543173

    work page doi:10.1109/tcsii.2025.3543173 2025

  2. [2]

    Analog Versus Digital: Extrapolating from Electronics to Neurobiology

    R. Sarpeshkar. “Analog Versus Digital: Extrapolating from Electronics to Neurobiology”. In: Neural Comput.10.7 (1998), pp. 1601–1638.doi:10.1162/089976698300017052

    work page doi:10.1162/089976698300017052 1998

  3. [3]

    Memory devices and applications for in-memory computing

    A. Sebastian et al. “Memory devices and applications for in-memory computing”. In:Nat. Nanotechnol.15.7 (2020), pp. 529–544.doi:10.1038/s41565-020-0655-z

    work page doi:10.1038/s41565-020-0655-z 2020

  4. [4]

    In-Memory Computing with Resistive Switching Devices

    D. Ielmini and H.-S. P. Wong. “In-Memory Computing with Resistive Switching Devices”. In: Nat. Electron.1.6 (2018), pp. 333–343.doi:10.1038/s41928-018-0092-2

    work page doi:10.1038/s41928-018-0092-2 2018

  5. [5]

    Hardware implementation of memristor-based artificial neural networks

    F. Aguirre et al. “Hardware implementation of memristor-based artificial neural networks”. In:Nat. Commun.15.1 (2024), p. 1974.doi:10.1038/s41467-024-45670-9

    work page doi:10.1038/s41467-024-45670-9 2024

  6. [6]

    Challenges and trends of SRAM-based computing-in-memory for AI edge devices

    C.-J. Jhang et al. “Challenges and trends of SRAM-based computing-in-memory for AI edge devices”. In:IEEE Trans. Circuits Syst. I68.5 (2021), pp. 1773–1786.doi: 10.1109/tcsi.2021.3064189

    work page doi:10.1109/tcsi.2021.3064189 2021

  7. [7]

    A review on SRAM-based computing in-memory: Circuits, functions, and applications

    Z. Lin et al. “A review on SRAM-based computing in-memory: Circuits, functions, and applications”. In:J. Semicond.43.3 (2022), p. 031401.doi: 10.1088/1674-4926/43/3/031401

    work page doi:10.1088/1674-4926/43/3/031401 2022

  8. [8]

    A fully integrated analogue closed-loop in-memory computing accelerator based on static random-access memory

    P. Mannocci et al. “A fully integrated analogue closed-loop in-memory computing accelerator based on static random-access memory”. In:Nat. Electron.(2026), pp. 1–13.doi: 10.1038/s41928-025-01549-1

    work page doi:10.1038/s41928-025-01549-1 2026

  9. [9]

    Which is the best dual-port SRAM in 45-nm process technology?—8T, 10T single end, and 10T differential

    H. Noguchi et al. “Which is the best dual-port SRAM in 45-nm process technology?—8T, 10T single end, and 10T differential”. In:2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial. IEEE. 2008, pp. 55–58.doi: 10.1109/icicdt.2008.4567245

    work page doi:10.1109/icicdt.2008.4567245 2008

  10. [10]

    Physics for neuromorphic computing

    D. Markovi´ c et al. “Physics for neuromorphic computing”. In:Nat. Rev. Phys.2.9 (2020), pp. 499–510.doi:10.1038/s42254-020-0208-2

    work page doi:10.1038/s42254-020-0208-2 2020

  11. [11]

    Accurate deep neural network inference using computational phase-change memory

    V. Joshi et al. “Accurate deep neural network inference using computational phase-change memory”. In:Nat. Commun.11.1 (2020), p. 2473.doi:10.1038/s41467-020-16108-9

    work page doi:10.1038/s41467-020-16108-9 2020

  12. [12]

    Variability-aware memristive crossbars—a tutorial

    A. P. James and L. O. Chua. “Variability-aware memristive crossbars—a tutorial”. In:IEEE Trans. Circuits Syst. II69.6 (2022), pp. 2570–2574.doi:10.1109/tcsii.2022.3169416

    work page doi:10.1109/tcsii.2022.3169416 2022

  13. [13]

    Research progress on solutions to the sneak path issue in memristor crossbar arrays

    L. Shi et al. “Research progress on solutions to the sneak path issue in memristor crossbar arrays”. In:Nanoscale Adv.2.5 (2020), pp. 1811–1827.doi:10.1039/d0na00100g

    work page doi:10.1039/d0na00100g 2020

  14. [14]

    A current-mode conductance-based silicon neuron for address-event neuromorphic systems

    P. Livi and G. Indiveri. “A current-mode conductance-based silicon neuron for address-event neuromorphic systems”. In:Proc. IEEE Int. Symp. Circuits Syst. (ISCAS). 2009, pp. 2898–2901.doi:10.1109/iscas.2009.5118408. 9 May 8, 2026 Preprint - A Fyon, L Mendoliaet al

    work page doi:10.1109/iscas.2009.5118408 2009

  15. [15]

    An ultra low power current-mode filter for neuromorphic systems and biomedical signal processing

    C. Bartolozzi, S. Mitra, and G. Indiveri. “An ultra low power current-mode filter for neuromorphic systems and biomedical signal processing”. In:Proc. IEEE Biomed. Circuits Syst. Conf. (BioCAS). 2006, pp. 130–133.doi:10.1109/biocas.2006.4600325

    work page doi:10.1109/biocas.2006.4600325 2006

  16. [16]

    2022 roadmap on neuromorphic computing and engineering

    D. V. Christensen et al. “2022 roadmap on neuromorphic computing and engineering”. In: Neuromorphic Comput. Eng.2.2 (2022), p. 022501.doi:10.1088/2634-4386/ac4a83

    work page doi:10.1088/2634-4386/ac4a83 2022

  17. [17]

    Spike-based local synaptic plasticity: A survey of computational models and neuromorphic circuits

    L. Khacef et al. “Spike-based local synaptic plasticity: A survey of computational models and neuromorphic circuits”. In:Neuromorphic Comput. Eng.3.4 (2023), p. 042001.doi: 10.1088/2634-4386/ad05da

    work page doi:10.1088/2634-4386/ad05da 2023

  18. [18]

    Opportunities for neuromorphic computing algorithms and applications

    C. D. Schuman et al. “Opportunities for neuromorphic computing algorithms and applications”. In:Nat. Comput. Sci.2.1 (2022), pp. 10–19.doi: 10.1038/s43588-021-00184-y

    work page doi:10.1038/s43588-021-00184-y 2022

  19. [19]

    Rubino et al.Neuromorphic analog circuits for robust on-chip always-on learning in spiking neural networks

    A. Rubino et al.Neuromorphic analog circuits for robust on-chip always-on learning in spiking neural networks. 2023. arXiv:2307.06084 [cs.NE]

    work page arXiv 2023

  20. [20]

    Neuromorphic computation with spiking memristors: habituation, experimental instantiation of logic gates and a novel sequence-sensitive perceptron model

    E. Gale. “Neuromorphic computation with spiking memristors: habituation, experimental instantiation of logic gates and a novel sequence-sensitive perceptron model”. In:Faraday Discuss.213 (2019), pp. 521–551.doi:10.1039/C8FD00111A

    work page doi:10.1039/c8fd00111a 2019

  21. [21]

    Construction of a spike-based memory using neural-like logic gates based on Spiking Neural Networks on SpiNNaker

    A. Ayuso-Martinez et al. “Construction of a spike-based memory using neural-like logic gates based on Spiking Neural Networks on SpiNNaker”. In:IEEE Trans. Emerg. Top. Comput.11 (2023), pp. 868–881.doi:10.1109/TETC.2023.3281063

    work page doi:10.1109/tetc.2023.3281063 2023

  22. [22]

    LogicSNN: A Unified Spiking Neural Networks Logical Operation Paradigm

    L. Mo and M. Wang. “LogicSNN: A Unified Spiking Neural Networks Logical Operation Paradigm”. In:Electronics10.17 (2021), p. 2123.doi:10.3390/electronics10172123

    work page doi:10.3390/electronics10172123 2021

  23. [23]

    Logic gates based on neuristors made from two-dimensional materials

    H. Chen et al. “Logic gates based on neuristors made from two-dimensional materials”. In: Nat. Electron.4.6 (2021), pp. 399–404.doi:10.1038/s41928-021-00591-z

    work page doi:10.1038/s41928-021-00591-z 2021

  24. [24]

    Logic-in-memory based on an atomically thin semiconductor

    G. Migliato Marega et al. “Logic-in-memory based on an atomically thin semiconductor”. In: Nature587.7832 (2020), pp. 72–77.doi:10.1038/s41586-020-2861-0

    work page doi:10.1038/s41586-020-2861-0 2020

  25. [25]

    CMOS Schmitt triggers

    B. L. Doki´ c. “CMOS Schmitt triggers”. In:IEE Proc. G131 (1984), pp. 197–202.doi: 10.1049/ip-g-1.1984.0037

    work page doi:10.1049/ip-g-1.1984.0037 1984

  26. [26]

    CMOS Schmitt trigger design

    I. M. Filanovsky and H. Baltes. “CMOS Schmitt trigger design”. In:IEEE Trans. Circuits Syst. I41.1 (2002), pp. 46–49.doi:10.1109/81.260219

    work page doi:10.1109/81.260219 2002

  27. [27]

    CMOS adjustable Schmitt triggers

    Z. Wang. “CMOS adjustable Schmitt triggers”. In:IEEE Trans. Instrum. Meas.40.3 (2002), pp. 601–605.doi:10.1109/19.87026

    work page doi:10.1109/19.87026 2002

  28. [28]

    A 160 mV robust Schmitt trigger based subthreshold SRAM

    J. P. Kulkarni, K. Kim, and K. Roy. “A 160 mV robust Schmitt trigger based subthreshold SRAM”. In:IEEE J. Solid-State Circuits42.10 (2007), pp. 2303–2313.doi: 10.1109/jssc.2007.897148

    work page doi:10.1109/jssc.2007.897148 2007

  29. [29]

    Parallelizable memory recurrent units

    F. De Geeter et al.Parallelizable memory recurrent units. 2026. arXiv:2601.09495 [cs.LG]

    work page internal anchor Pith review Pith/arXiv arXiv 2026

  30. [30]

    Improving the Performance and Learning Stability of Parallelizable RNNs Designed for Ultra-Low Power Applications

    J. Brandoit et al.Improving the Performance and Learning Stability of Parallelizable RNNs Designed for Ultra-Low Power Applications. 2026. arXiv:2605.11855 [cs.LG]

    work page internal anchor Pith review Pith/arXiv arXiv 2026

  31. [31]

    Hardware-Software Co-Design of Scalable, Energy-Efficient Analog Recurrent Computations

    A. Fyon et al.Hardware-Software Co-Design of Scalable, Energy-Efficient Analog Recurrent Computations. 2026. arXiv:2605.15216 [cs.AR]

    work page internal anchor Pith review Pith/arXiv arXiv 2026

  32. [32]

    A fully/electronically controllable voltage-mode Schmitt trigger based on only single VDGA and its applications

    M. Siripruchyanun and J. Hirunporm. “A fully/electronically controllable voltage-mode Schmitt trigger based on only single VDGA and its applications”. In:AEU - Int. J. Electron. Commun.131 (2021), p. 153602.doi:10.1016/j.aeue.2020.153602

    work page doi:10.1016/j.aeue.2020.153602 2021

  33. [33]

    Novel CMOS Schmitt trigger

    M. Steyaert and W. Sansen. “Novel CMOS Schmitt trigger”. In:Electron. Lett.22.4 (1986), pp. 203–204.doi:10.1049/el:19860142

    work page doi:10.1049/el:19860142 1986

  34. [34]

    Novel approach to high-speed CMOS current comparators

    H. Traff. “Novel approach to high-speed CMOS current comparators”. In:Electron. Lett.28.3 (1992), pp. 310–311.doi:10.1049/el:19920192

    work page doi:10.1049/el:19920192 1992

  35. [35]

    OTA-R Schmitt trigger with independently controllable threshold and output voltage levels

    K. Kim, H.-W. Cha, and W.-S. Chung. “OTA-R Schmitt trigger with independently controllable threshold and output voltage levels”. In:Electron. Lett.33.13 (1997), pp. 1103–1105.doi:10.1049/el:19970786

    work page doi:10.1049/el:19970786 1997

  36. [36]

    Single CDBA-based voltage-mode bistable multivibrator and its applications

    R. Pal et al. “Single CDBA-based voltage-mode bistable multivibrator and its applications”. In:Circuits Syst.6.11 (2015), pp. 237–251.doi:10.4236/cs.2015.611024

    work page doi:10.4236/cs.2015.611024 2015

  37. [37]

    A novel current conveyor-based Schmitt trigger and its application as a relaxation oscillator

    A. Srinivasulu. “A novel current conveyor-based Schmitt trigger and its application as a relaxation oscillator”. In:Int. J. Circuit Theory Appl.39.6 (2011), pp. 679–686.doi: 10.1002/cta.669. 10 May 8, 2026 Preprint - A Fyon, L Mendoliaet al

    work page doi:10.1002/cta.669 2011

  38. [38]

    A simple fully controllable Schmitt trigger with electronic method using VDTA

    M. Siripruchyanun, P. Satthaphol, and K. Payakkakul. “A simple fully controllable Schmitt trigger with electronic method using VDTA”. In:Appl. Mech. Mater.781 (2015), pp. 180–183.doi:10.4028/www.scientific.net/amm.781.180

    work page doi:10.4028/www.scientific.net/amm.781.180 2015

  39. [39]

    Novel CMOS current Schmitt trigger

    Z. Wang and W. Guggenbohl. “Novel CMOS current Schmitt trigger”. In:Electron. Lett. 24.24 (1988), pp. 1514–1516.doi:10.1049/el:19881034

    work page doi:10.1049/el:19881034 1988

  40. [40]

    A high-speed differential CMOS Schmitt trigger with regenerative current feedback and adjustable hysteresis

    F. Yuan. “A high-speed differential CMOS Schmitt trigger with regenerative current feedback and adjustable hysteresis”. In:Analog Integr. Circuits Signal Process.63.1 (2010), pp. 121–127.doi:10.1007/s10470-009-9374-y

    work page doi:10.1007/s10470-009-9374-y 2010

  41. [41]

    Low-voltage subthreshold CMOS current mode circuits: Design and applications

    M. A. Eldeeb et al. “Low-voltage subthreshold CMOS current mode circuits: Design and applications”. In:AEU-Int. J. Electron. Commun.82 (2017), pp. 251–264.doi: 10.1016/j.aeue.2017.08.049

    work page doi:10.1016/j.aeue.2017.08.049 2017

  42. [42]

    A current-mode Schmitt trigger based on current differencing transconductance amplifier

    T. Srivyshnavi and A. Srinivasulu. “A current-mode Schmitt trigger based on current differencing transconductance amplifier”. In:Proc. IEEE Int. Conf. Signal Process., Commun. Netw. (ICSCN). 2015, pp. 1–4.doi:10.1109/icscn.2015.7219884

    work page doi:10.1109/icscn.2015.7219884 2015

  43. [43]

    Novel electronically controlled current-mode Schmitt trigger based on single active element

    A. Kumar and B. Chaturvedi. “Novel electronically controlled current-mode Schmitt trigger based on single active element”. In:AEU - Int. J. Electron. Commun.82 (2017), pp. 160–166.doi:10.1016/j.aeue.2017.08.007

    work page doi:10.1016/j.aeue.2017.08.007 2017

  44. [44]

    A simple current-mode Schmitt trigger employing only single MO-CTTA

    P. Silapan and M. Siripruchyanun. “A simple current-mode Schmitt trigger employing only single MO-CTTA”. In:Proc. 6th IEEE Int. Conf. Electr. Eng./Electron., Comput., Telecommun. Inf. Technol. (ECTI-CON). 2009, pp. 556–559.doi: 10.1109/ecticon.2009.5137068

    work page doi:10.1109/ecticon.2009.5137068 2009

  45. [45]

    Fully and electronically controllable current-mode Schmitt triggers employing only single MO-CCCDTA and their applications

    P. Silapan and M. Siripruchyanun. “Fully and electronically controllable current-mode Schmitt triggers employing only single MO-CCCDTA and their applications”. In:Analog Integr. Circuits Signal Process.68.1 (2011), pp. 111–128.doi:10.1007/s10470-010-9593-2

    work page doi:10.1007/s10470-010-9593-2 2011

  46. [46]

    Current-mode Schmitt trigger based on ZC-current differencing transconductance amplifier

    S. Madira, V. V. Reddy, and A. Srinivasulu. “Current-mode Schmitt trigger based on ZC-current differencing transconductance amplifier”. In:Proc. IEEE Int. Conf. Inventive Comput. Technol. (ICICT). 2016, pp. 1–5.doi:10.1109/inventive.2016.7823226

    work page doi:10.1109/inventive.2016.7823226 2016

  47. [47]

    A Schmitt trigger based on DDCCTA without any passive components

    R. Linitha, A. Srinivasulu, and V. V. Reddy. “A Schmitt trigger based on DDCCTA without any passive components”. In:Proc. IEEE Int. Conf. Commun. Signal Process. (ICCSP). 2015, pp. 1695–1698.doi:10.1109/iccsp.2015.7322808

    work page doi:10.1109/iccsp.2015.7322808 2015

  48. [48]

    A. N. Mazumder and T. Mohsenin.A fast network exploration strategy to profile low energy consumption for keyword spotting. 2022. arXiv:2202.02361 [cs.LG]

    work page arXiv 2022

  49. [49]

    Mlperf tiny benchmark.arXiv preprint arXiv:2106.07597, 2021a

    C. Banbury et al.MLPerf Tiny Benchmark. 2021. arXiv:2106.07597 [cs.LG]

    work page arXiv 2021

  50. [50]

    MCUNet: Tiny Deep Learning on IoT Devices

    J. Lin et al. “MCUNet: Tiny Deep Learning on IoT Devices”. In:Advances in Neural Information Processing Systems. Vol. 33. Virtual, 2020, pp. 11711–11722

    work page 2020

  51. [51]

    Hello Edge: Keyword Spotting on Microcontrollers

    Y. Zhang et al.Hello Edge: Keyword Spotting on Microcontrollers. 2017. arXiv:1711.07128 [cs.SD]. 11

    work page internal anchor Pith review Pith/arXiv arXiv 2017