Paper Citation Record · LEDGER

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code

As of 7 August 2026, this Paper Citation Record lists 25 of 25 outbound references and 0 inbound Pith citation observations for arXiv:2509.08416.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2509.08416 v1

Coverage vector

measured 25 of 25 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-04T20:43:15.537043Z

measured 25 of 25 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

25 of 25 outbound references displayed

verified exact0
verified fuzzy9
unresolved16
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation d05f82ea-66c2-4746-89a6-65c24daa60ba · outbound

This paper cites On the robustness of code generation techniques: An empirical study on github copilot,.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code On the robustness of code generation techniques: An empirical study on github copilot,

Reference 1

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:12.855918Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b18a651e-8e80-4c51-8f7f-54cd1b9f41f2 · outbound

This paper cites CodeGen2: Lessons for Training LLMs on Programming and Natural Languages.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code CodeGen2: Lessons for Training LLMs on Programming and Natural Languages

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:12.940366Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 337e701e-068f-4a0b-ac2f-93e57f87aa46 · outbound

This paper cites Benchmarking large language models for automated verilog rtl code generation,.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Benchmarking large language models for automated verilog rtl code generation,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-04T20:43:17.317961Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation a42ed1ab-3222-47a1-a07e-ef6f8639baf4 · outbound

This paper cites A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:13.097994Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ff5e74b4-38f6-4fb7-a555-9ce7e44f9524 · outbound

This paper cites Openllm-rtl: Open dataset and benchmark for llm-aided design rtl generation(invited),.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Openllm-rtl: Open dataset and benchmark for llm-aided design rtl generation(invited),

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-04T20:43:17.301351Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 61d475c9-4d1b-4de9-a9fa-b7495ded2cc0 · outbound

This paper cites Verilogeval: Evaluating large language models for verilog code generation,.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Verilogeval: Evaluating large language models for verilog code generation,

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:13.271417Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ec083c87-0660-4c5a-a67e-0da04ca7ae19 · outbound

This paper cites Rtlcoder: Outperforming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution,.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Rtlcoder: Outperforming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-04T20:43:17.274735Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation f770b0c3-672a-47a9-a917-7c635ec85a49 · outbound

This paper cites OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:13.447783Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a2885405-6376-4d5e-92b7-bba5f3e98367 · outbound

This paper cites Evaluating Large Language Models Trained on Code.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Evaluating Large Language Models Trained on Code

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:13.568782Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 81053871-d0f4-485d-94aa-d42267425767 · outbound

This paper cites AutoChip: Automating HDL Generation Using LLM Feedback.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code AutoChip: Automating HDL Generation Using LLM Feedback

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:13.684192Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ba2e1215-8d73-4ce5-88c8-51f7f73c19c1 · outbound

This paper cites Rtlfixer: Automatically fixing rtl syntax errors with large language model,.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Rtlfixer: Automatically fixing rtl syntax errors with large language model,

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:13.793486Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation beb07df9-a0a9-413c-aaa0-debd7014c7b9 · outbound

This paper cites VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:13.889616Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c009b431-ea1e-4a87-a9a2-a509ac58bf19 · outbound

This paper cites Myhdl: A python-based hardware description language,.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Myhdl: A python-based hardware description language,

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-04T20:43:17.142671Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 8d9200e6-7a2c-4206-9556-3d8a80972feb · outbound

This paper cites Exploiting computation reuse for stencil acceler- ators,.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Exploiting computation reuse for stencil acceler- ators,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-04T20:43:16.919860Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation c91e2155-1fd0-4cf1-8d63-646b441bab22 · outbound

This paper cites BetterV: Controlled Verilog Generation with Discriminative Guidance.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:14.334778Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 178ef397-ecb0-443f-aa56-ae5b3c09b8e5 · outbound

This paper cites Verigen: A large language model for verilog code generation,.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Verigen: A large language model for verilog code generation,

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:14.477090Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b71476eb-7adb-4eca-9d46-b8b4e4d32622 · outbound

This paper cites CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesis.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesis

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:14.599727Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8e04e80e-1817-4379-8a36-266ce86e7cc3 · outbound

This paper cites Gpt-3.5-turbo,.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Gpt-3.5-turbo,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-04T20:43:16.627275Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 9b62a560-c9a9-49fe-a68e-1b159661ab73 · outbound

This paper cites Gpt-4 technical report,.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Gpt-4 technical report,

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-04T20:43:16.329709Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation a1ed3f52-0ac1-499f-8d6e-1487f5a74620 · outbound

This paper cites Rtllm: An open-source benchmark for design rtl generation with large language model,.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Rtllm: An open-source benchmark for design rtl generation with large language model,

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:15.047617Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1080c7ad-84cd-42fe-827c-acce934cd4c5 · outbound

This paper cites A multi-expert large language model archi- tecture for verilog code generation,.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code A multi-expert large language model archi- tecture for verilog code generation,

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-04T20:43:16.040097Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ac223382-04e0-43a9-9621-67a493033bea · outbound

This paper cites Code Llama: Open Foundation Models for Code.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Code Llama: Open Foundation Models for Code

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:15.254197Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f9e7f84b-2376-4795-86d2-908afff8719f · outbound

This paper cites Qwen Technical Report.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Qwen Technical Report

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:15.308227Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 85dcc5e9-065b-4c48-8546-345d86232559 · outbound

This paper cites DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligence.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligence

Reference 24

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:15.416267Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 906c4bdf-6852-413d-b50e-fc3265afd0d2 · outbound

This paper cites Introducing the next generation of claude,.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code Introducing the next generation of claude,

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-04T20:43:15.891949Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Pith citing papers

No inbound Pith citation observations are available.