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3D-Integrated Superconducting qubits: CMOS-Compatible, Wafer-Scale Processing for Flip-Chip Architectures

T0 review · 2 major / 5 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read Working superconducting qubits made with CMOS-compatible, 200 mm wafer processing and connected by a new Si-island microbump that transfers control signals with negligible added loss.

desk verdict A credible 200 mm CMOS-compatible flip-chip qubit process with a genuinely new Si-island microbump technology, but the 'negligible loss' claim is not quantitatively supported and may conflict with the residual 20 Ω DC resistance. read the letter →

arxiv 2505.04337 v3 pith:ZQBURKH6 submitted 2025-05-07 quant-ph

T. Mayer , H. Bender , S.J.K. Lang , Z. Luo , J. Weber , C. Moran Guizan , C. Dhieb , D. Zahn
show 11 more authors
L. Schwarzenbach W. Hell M. Andronic A. Drost K. Neumeier W. Lerch L. Nebrich A. Hagelauer I. Eisele R.N. Pereira C. Kutter
This is my paper · ORCID
classification quant-ph
keywords superconductingqubitsflip-chipbonding3DintegrationCMOS-compatiblefabricationmicrobumpswafer-scaleprocessingtransmoncoherencetime
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper demonstrates that superconducting qubits can be fabricated entirely in a CMOS-compatible, 200 mm wafer process using subtractive etching, then 3D-integrated by flipping the chip onto a carrier and connecting them with tiny metallized silicon-island bumps. The authors report that the bump connection is superconducting in its metal stacks, that radio-frequency signals pass through it with no measurable extra loss, and that 29 out of 31 tested qubit/resonator pairs showed working qubit signatures with energy relaxation times up to 15 microseconds. If this holds, it opens a route to making quantum processors on the same large-wafer infrastructure that produces conventional computer chips, while also providing the chip-to-chip wiring that larger, modular quantum processors will need.

What carries the argument

The central object is the Si-island microbump: a KOH-etched silicon pillar on the carrier chip, metallized with a Nb/In stack, that bonds to a TiN/In pad on the qubit chip. The silicon island sets a precise, reproducible chip-to-chip spacing while providing both a dense grid of grounding connections and the two RF signal connections at the ends of each feedline. The second load-bearing element is the all-subtractive Josephson junction process, which replaces double-angle evaporation and lift-off with two optical lithography layers and dry etching, making the qubit fabrication compatible with CMOS contamination rules and 200 mm tooling.

What would settle it

In the same cooldown and with the same calibration, measure the S21 of a flip-chip feedline and a co-fabricated planar CPW through-line of identical length; if the flip-chip path drops by more than a few tenths of a dB relative to the planar reference, the claim of negligible added loss fails. A time-domain reflectometry trace that shows a discrete reflection at the bump would also falsify it.

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Extended reading notes

Core claim

The paper claims that a proof-of-concept device hosting 24 fixed-frequency transmons on a 12.3 mm qubit chip, flip-chip bonded to a 14.3 mm carrier chip, works as a functional 3D-integrated superconducting quantum processor. The qubit chip and carrier are fabricated on separate 200 mm wafers using industry-style, subtractive processing (including an all-dry-etched aluminum Josephson junction instead of shadow-mask lift-off), and the connection between chips is made by an array of Si-island microbumps with Nb/In on the carrier side and TiN/In pads on the qubit side. Measurements show the bumps become superconducting with transitions near the expected critical temperatures, RF transmission through the bump-connected feedline is comparable to standard planar coplanar waveguide lines, and of 31 measurable resonator/qubit pairs, 29 produce clear qubit signatures, with T1 up to 15 µs and T2* up to 17 µs.

Load-bearing premise

The claim that the microbump adds negligible RF loss rests on a qualitative comparison of the measured transmission to standard planar lines, while DC measurements show about 20 ohms of residual resistance in the bump path at base temperature; if that residual resistance causes appreciable insertion loss at the 4-8 GHz operating band, the central claim about the interconnect weakens.

Editorial extensions

If this is right

  • Qubit production can move onto the same 200 mm lithography, etch, and deposition tools used for conventional CMOS chips, improving wafer-scale uniformity and repeatability.
  • The microbump interconnect can replace airbridges for uniform grounding and can route control signals across chip boundaries, enabling signal crossings in complex QPU layouts.
  • With 151 qubit chips per wafer and 119 carrier chips per wafer, the process is directly compatible with modular, chiplet-style quantum processors in which several qubit dies are bonded to one carrier.
  • The reported coherence times come from the very first processing run, so subsequent runs should improve as the microbump metallurgy and interfaces are optimized.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A quantitative S21 comparison against a calibrated on-chip reference line would settle whether the unquantified 'negligible attenuation' claim holds; the paper's current evidence is suggestive but not metrological.
  • If the roughly 20 Ω residual DC resistance arises from a thin normal-metallic TiN layer, its effect could be frequency- or power-dependent and may show up in resonator quality factors at higher drive powers, which the present measurements do not resolve.
  • The Si-island gap-control technique could transfer to other multi-chip platforms, such as spin-qubit or photonic modules, that need accurate and reproducible die-to-die spacing.
  • A direct test of the claim that the bumps eliminate the need for airbridges would be to compare coherence on the same chip layout with and without additional wirebond or airbridge grounding.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. The manuscript reports a proof-of-concept development of superconducting transmon qubits fabricated on 200 mm wafers using CMOS-line equipment with subtractive patterning of Al/AlOx/Al Josephson junctions, and 3D-integrated to a carrier chip via flip-chip bonding using metallized KOH-etched Si-island microbumps. DC measurements of the bump/feedline path show superconducting transitions of Nb, In, and Al but a residual ~20 Ω at 10 mK; calibrated S21 measurements are claimed to show transmission comparable to planar CPW with negligible added loss. In qubit characterization across six feedlines on four assemblies, 29/31 qubit-resonator pairs showed one- and two-tone spectroscopy signatures, with T1 up to 15 μs and T2* up to 17 μs.

Significance. If the quantitative claims were fully supported, the work would be of practical significance: it demonstrates that industry-style 200 mm wafer processing and flip-chip integration can produce functional transmon qubits in a first run, with a path toward large-area grounding and signal routing without airbridges. The strengths are the direct measurements of a complete integrated device, the explicit reporting of yield statistics (31/36 resonators, 29/31 qubits), and the transparent statement that full superconductivity of the bump path was not achieved. The paper is a process/technology demonstration rather than a coherence-optimization study; T1 ~15 μs is modest compared to state-of-the-art planar qubits but reasonable for a first integrated run. The central claims are direct measurements; there is no fitted derivation, and the reliance on companion papers for design details does not create circularity.

major comments (2)
  1. [Sec. V.A, Fig. 4; Sec. VI] The abstract claim that 'the microbump connection in the signal chain is not introducing additional insertion loss' is not quantitatively established. The DC measurement in Fig. 4a shows a residual resistance of about 20 Ω at 10 mK, and Sec. VI concedes that full superconductivity of the bump path was not reached. If this residual resistance were in series in the 50 Ω feedline, it alone would produce roughly 20log10(2Z0/(2Z0+R)) ≈ -1.6 dB of insertion loss, which is not negligible at the level claimed. The S21 trace in Fig. 4b is compared only qualitatively to "standard planar CPW signal lines," with no reference trace on the same chip, no loss-per-length or equivalent-circuit fit, and no stated error or reproducibility. Because the low-loss RF interconnect is the principal novelty of the bump technology, this point must be supported by a quantitative check, e.g., a direct comparison with a reference planar CPW line of the same length on the same carrier, or a model using the measured residual resistance and surface impedance that reproduces the S21.
  2. [Sec. V.B and Abstract] The 'high yield' claim is based on measurements of six feedlines on four assemblies that were chosen for wire-bonding and mounting. The paper does not state the selection criterion, the total number of bonded devices produced, or how many devices failed before measurement. Without that information, the reported 29/31 qubit yield cannot be interpreted as a process yield or representative yield; it may reflect a favorable subset. Please report the selection procedure and, if possible, statistics over a larger set of devices, or weaken the claim to 'in the measured devices.'
minor comments (5)
  1. [Sec. I] The first sentence contains a typo: "multiple advantages ... the make it" should read "that make it."
  2. [Sec. V.A, Fig. 4b] The shaded region in Fig. 4b is described as "the relevant frequency range of 4–8 GHz" in the text, but the figure caption does not define it, and the expected baseline insertion loss for a planar CPW line of the same length is not given; please add this information to make the comparison concrete.
  3. [Sec. III.A] The description of the TiN/In lift-off processing is somewhat ambiguous: the text says the resist is exposed again by i-line stepper lithography and then states that the lift-off resist is exposed to ion bombardment; please clarify whether the same resist layer is used and how the surface preparation avoids degrading the lift-off profile.
  4. [Sec. V.B] The phrase "time-domain spectroscopy" is non-standard for pulsed T1 and T2* measurements; consider using "time-domain measurements" or "pulsed qubit characterization."
  5. [Refs. [13] and [16]] Essential design and process details are delegated to companion papers [13] and [16]; since the main claims should be assessable from the present manuscript, please include the key circuit parameters (qubit frequencies, anharmonicities, and feedline/resonator geometry) in the main text or supplement.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: all load-bearing claims are direct measurements; self-citations are background only.

full rationale

This is an experimental process-development paper. The central claims—the superconducting transition of the bump metal stacks, RF signal transfer through the microbump with negligible attenuation, and high-yield qubit excitation with T1 up to 15 µs—are supported by direct measurements (Fig. 4 and Fig. 5), not by a derivation from assumptions or by fitted parameters. The 'negligible attenuation' statement in Sec. V.A rests on a qualitative visual comparison of calibrated S21 to 'standard planar CPW signal lines' with no reference trace or error budget, and the residual ~20 Ω DC resistance noted in Fig. 4a is acknowledged in Sec. VI ('no full superconductivity of the bumps'). These are quantitative-support weaknesses (correctness risk), not circularity: the claim is not defined in terms of itself, and no fitted input is renamed as a prediction. Refs. [13] and [16] are the authors' companion papers, but they are cited only for chip-design/circuit-modelling details and for prior planar-process performance; the present qubit and bump results are independently measured in this work. No derivation chain reduces Eq. X to Eq. Y by construction, so no circular step is identified.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

The central claims rest on direct measurements rather than derived models, so no free parameters or invented entities apply. The listed axioms capture the interpretation steps that turn raw traces into the paper's conclusions: the qualitative RF comparison, the spectroscopic definition of qubit yield, and the attribution of the residual resistance to interfaces.

assumptions (3)
  • domain assumption The measured S21 through the bump chain is comparable to a standard planar CPW line, so the bump adds negligible insertion loss.
    Sec. V.A, Fig. 4b. The paper provides no quantitative reference trace or uncertainty analysis for this comparison.
  • domain assumption Qubit signatures in one- and two-tone spectroscopy (punch-out and response at a second frequency) certify a functional qubit.
    Sec. V.B. No Rabi oscillations, calibrations, or gate operations are shown; the yield count (29/31) relies on these spectroscopic signatures.
  • domain assumption The residual ~20 ohm resistance at base temperature arises from interface oxides (e.g., AlOx at Al/TiN) rather than a lossy element that would affect RF performance.
    Sec. V.A. The authors present this as 'a more likely explanation' without direct evidence.

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Cite this review

Pith. "Pith review of 3D-Integrated Superconducting qubits: CMOS-Compatible, Wafer-Scale Processing for Flip-Chip Architectures." pith.science (2026). https://pith.science/paper/ZQBURKH6

@misc{pith2026250504337,
  author       = {Pith},
  title        = {Pith review of: 3D-Integrated Superconducting qubits: CMOS-Compatible, Wafer-Scale Processing for Flip-Chip Architectures},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ZQBURKH6}},
  note         = {Machine review of arXiv:2505.04337}
}
read the original abstract

In this article, we present a technology development of a superconducting qubit device 3D-integrated by flip-chip-bonding and processed following CMOS fabrication standards and contamination rules on 200 mm wafers. We present the utilized proof-of-concept chip designs for qubit- and carrier chip, as well as the respective front-end and back-end fabrication techniques. In characterization of the newly developed microbump technology based on metallized KOH-etched Si-islands, we observe a superconducting transition of the used metal stacks and radio frequency (RF) signal transfer through the bump connection with negligible attenuation. In time-domain spectroscopy of the qubits we find high yield qubit excitation with energy relaxation times of up to 15 us.

Figures

Figures reproduced from arXiv: 2505.04337 by the authors.

Figure 1
Figure 1. FIG. 1: Micrograph of qubit chip (a) and carrier chip (b). Larger magnification images of the respective chips c) - f). [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2: Scanning Electron Microscopy images of various processing stages. Finished Josephson Junction (a), [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3: Schematic drawing visualizing the chip-to-chip [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: FIG. 4: Measurements of superconductivity of the [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: FIG. 5: Exemplary measurements for one-tone (a) and two-tone (b) spectroscopy and for [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]

Discussion (0). Continue with ORCID to comment.

Forward citations

Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Stability studies on subtractively-fabricated CMOS-compatible superconducting transmon qubits

    quant-ph 2025-12 conditional novelty 6.0 of 10

    Subtractively-fabricated CMOS-compatible transmon qubits show T1 stability on par with lift-off qubits, with a universal σT1 ∝ ⟨T1⟩^{3/2} scaling and a few-percent junction aging over a year.

  2. CMOS-Compatible, Wafer-Scale Processed Superconducting Qubits Exceeding Energy Relaxation Times of 200us

    quant-ph 2025-05 conditional novelty 5.0 of 10

    A 200 mm CMOS-compatible subtractive process produced transmon qubits with median T1 near 100 microseconds and individual qubits exceeding 200 microseconds, the best reported for wafer-level subtractive fabrication.

Reference graph

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