Agents that route PCBs through KiCad's native API with design-rule feedback outperform grid-action RL and open-loop LLM baselines, and a synthetic-trained PPO transfers zero-shot to real boards.
Rtlfixer: Automatically fixing rtl syntax errors with large language models
10 Pith papers cite this work, alongside 10 external citations. Polarity classification is still indexing.
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abstract
This paper presents RTLFixer, a novel framework enabling automatic syntax errors fixing for Verilog code with Large Language Models (LLMs). Despite LLM's promising capabilities, our analysis indicates that approximately 55% of errors in LLM-generated Verilog are syntax-related, leading to compilation failures. To tackle this issue, we introduce a novel debugging framework that employs Retrieval-Augmented Generation (RAG) and ReAct prompting, enabling LLMs to act as autonomous agents in interactively debugging the code with feedback. This framework demonstrates exceptional proficiency in resolving syntax errors, successfully correcting about 98.5% of compilation errors in our debugging dataset, comprising 212 erroneous implementations derived from the VerilogEval benchmark. Our method leads to 32.3% and 10.1% increase in pass@1 success rates in the VerilogEval-Machine and VerilogEval-Human benchmarks, respectively.
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ProofLoop achieves 93.7% syntax correctness and 82.0% functional correctness for SVA generation from natural language by combining retrieval, EDA tools, and up to three rounds of JasperGold formal feedback.
Clover fixes 96.8% of bugs on an RTL-repair benchmark using stochastic tree-of-thoughts and neural-symbolic agents, outperforming traditional and LLM baselines by 94% and 63% respectively with 87.5% pass@1.
Verilog-Evolve uses executable feedback from simulation, synthesis, timing, and GEMM metrics to refine LLM-generated Verilog and evolves skills across tasks, improving functional success and downstream hardware quality on VerilogEval and mixed-precision GEMM benchmarks.
An agentic LLM system produces functionally correct obfuscated netlists on ISCAS-85 benchmarks that cause output corruption with wrong keys but remain breakable by SAT attacks.
FVRuleLearner retrieves learned operator-level reasoning rules to boost the functional correctness of LLM-generated SystemVerilog assertions by roughly 30 percentage points over simple prompting baselines.
UVM^2 is an LLM-driven system that generates and refines UVM testbenches for RTL verification, reporting up to substantial time savings and average code/function coverage of 87.44%/89.58% on designs up to 1.6K lines, outperforming prior methods.
A survey classifying RAG foundations for AIGC, summarizing enhancements, cross-modal applications, benchmarks, limitations, and future directions.
HORIZON applies repository-level self-evolution to hardware design artifacts and reports 100% completion on ChipBench, RTLLM, Verilog-Eval, and nine CVDP categories using a hands-free agent loop.
A systematic review of memory designs, evaluation methods, applications, limitations, and future directions for LLM-based agents.
citing papers explorer
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PCBWorld: A Benchmark Environment for Engine-Grounded PCB Design Automation
Agents that route PCBs through KiCad's native API with design-rule feedback outperform grid-action RL and open-loop LLM baselines, and a synthetic-trained PPO transfers zero-shot to real boards.
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From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation
ProofLoop achieves 93.7% syntax correctness and 82.0% functional correctness for SVA generation from natural language by combining retrieval, EDA tools, and up to three rounds of JasperGold formal feedback.
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Clover: A Neural-Symbolic Agentic Harness with Stochastic Tree-of-Thoughts for Verified RTL Repair
Clover fixes 96.8% of bugs on an RTL-repair benchmark using stochastic tree-of-thoughts and neural-symbolic agents, outperforming traditional and LLM baselines by 94% and 63% respectively with 87.5% pass@1.
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Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation
Verilog-Evolve uses executable feedback from simulation, synthesis, timing, and GEMM metrics to refine LLM-generated Verilog and evolves skills across tasks, improving functional success and downstream hardware quality on VerilogEval and mixed-precision GEMM benchmarks.
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Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection
An agentic LLM system produces functionally correct obfuscated netlists on ISCAS-85 benchmarks that cause output corruption with wrong keys but remain breakable by SAT attacks.
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FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification
FVRuleLearner retrieves learned operator-level reasoning rules to boost the functional correctness of LLM-generated SystemVerilog assertions by roughly 30 percentage points over simple prompting baselines.
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From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
UVM^2 is an LLM-driven system that generates and refines UVM testbenches for RTL verification, reporting up to substantial time savings and average code/function coverage of 87.44%/89.58% on designs up to 1.6K lines, outperforming prior methods.
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Retrieval-Augmented Generation for AI-Generated Content: A Survey
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Agentic Hardware Design as Repository-Level Code Evolution
HORIZON applies repository-level self-evolution to hardware design artifacts and reports 100% completion on ChipBench, RTLLM, Verilog-Eval, and nine CVDP categories using a hands-free agent loop.
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A Survey on the Memory Mechanism of Large Language Model based Agents
A systematic review of memory designs, evaluation methods, applications, limitations, and future directions for LLM-based agents.