ProofLoop achieves 93.7% syntax correctness and 82.0% functional correctness for SVA generation from natural language by combining retrieval, EDA tools, and up to three rounds of JasperGold formal feedback.
Rtlfixer: Automatically fixing rtl syntax errors with large language models
9 Pith papers cite this work. Polarity classification is still indexing.
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Clover fixes 96.8% of bugs on an RTL-repair benchmark using stochastic tree-of-thoughts and neural-symbolic agents, outperforming traditional and LLM baselines by 94% and 63% respectively with 87.5% pass@1.
FVRuleLearner introduces an Operator Reasoning Tree to learn operator-specific rules that improve natural-language to SystemVerilog assertion generation, raising syntax correctness by 3.95% and functional correctness by 31.17% over baselines.
Verilog-Evolve uses executable feedback from simulation, synthesis, timing, and GEMM metrics to refine LLM-generated Verilog and evolves skills across tasks, improving functional success and downstream hardware quality on VerilogEval and mixed-precision GEMM benchmarks.
An agentic LLM system produces functionally correct obfuscated netlists on ISCAS-85 benchmarks that cause output corruption with wrong keys but remain breakable by SAT attacks.
UVM^2 is an LLM-driven system that generates and refines UVM testbenches for RTL verification, reporting up to substantial time savings and average code/function coverage of 87.44%/89.58% on designs up to 1.6K lines, outperforming prior methods.
A survey classifying RAG foundations for AIGC, summarizing enhancements, cross-modal applications, benchmarks, limitations, and future directions.
HORIZON applies repository-level self-evolution to hardware design artifacts and reports 100% completion on ChipBench, RTLLM, Verilog-Eval, and nine CVDP categories using a hands-free agent loop.
A systematic review of memory designs, evaluation methods, applications, limitations, and future directions for LLM-based agents.
citing papers explorer
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From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation
ProofLoop achieves 93.7% syntax correctness and 82.0% functional correctness for SVA generation from natural language by combining retrieval, EDA tools, and up to three rounds of JasperGold formal feedback.
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Clover: A Neural-Symbolic Agentic Harness with Stochastic Tree-of-Thoughts for Verified RTL Repair
Clover fixes 96.8% of bugs on an RTL-repair benchmark using stochastic tree-of-thoughts and neural-symbolic agents, outperforming traditional and LLM baselines by 94% and 63% respectively with 87.5% pass@1.
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FVRuleLearner: Operator-Level Reasoning Tree (OP-Tree)-Based Rules Learning for Formal Verification
FVRuleLearner introduces an Operator Reasoning Tree to learn operator-specific rules that improve natural-language to SystemVerilog assertion generation, raising syntax correctness by 3.95% and functional correctness by 31.17% over baselines.
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Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation
Verilog-Evolve uses executable feedback from simulation, synthesis, timing, and GEMM metrics to refine LLM-generated Verilog and evolves skills across tasks, improving functional success and downstream hardware quality on VerilogEval and mixed-precision GEMM benchmarks.
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Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection
An agentic LLM system produces functionally correct obfuscated netlists on ISCAS-85 benchmarks that cause output corruption with wrong keys but remain breakable by SAT attacks.
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Agentic Hardware Design as Repository-Level Code Evolution
HORIZON applies repository-level self-evolution to hardware design artifacts and reports 100% completion on ChipBench, RTLLM, Verilog-Eval, and nine CVDP categories using a hands-free agent loop.