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arxiv: 2510.05221 · v2 · submitted 2025-10-06 · 🪐 quant-ph

Fault-tolerant interfaces for modular quantum computing on diverse qubit platforms

Frederik K. Marqversen , Gefen Baranes , Maxim Sirotin , Johannes Borregaard This is my paper

Pith reviewed 2026-05-18 09:04 UTC · model grok-4.3

classification 🪐 quant-ph
keywords fault-tolerant interfacesmodular quantum computingsurface codelattice surgerytransversal gateslogical error ratesqubit platformsquantum error correction
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The pith

Optimal fault-tolerant interfaces for modular quantum computers depend on hardware parameters such as gate fidelity and entangling rate.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper examines how to link smaller quantum processors into a larger fault-tolerant system. It compares known methods like lattice surgery and transversal gates against new grow-and-distil protocols that combine code growth with logical distillation. Modeling all approaches inside the surface code reveals which strategy minimizes overhead for given values of gate error, connection speed, and available memory. The work then calculates the hardware specifications needed to reach logical error rates of 10^{-6} and 10^{-12}. This matters because modular architectures are viewed as the most practical route to scaling quantum computers beyond single-device limits.

Core claim

Using the surface code, we identify optimal interface strategies across a wide range of hardware parameters, such as gate fidelities, entangling rates, and memory resources, and estimate the requirements to achieve logical error rates of 10^{-6} and 10^{-12}. Our results establish when the interface becomes a bottleneck in the computation and provide guidance for experimental implementations with superconducting, atomic, and solid-state hardware.

What carries the argument

Surface-code comparison of lattice surgery, transversal gates, and grow-and-distil protocols, which selects the lowest-overhead method for each combination of gate fidelity, entangling rate, and memory resources.

If this is right

  • The interface becomes the dominant error source once hardware parameters fall below the thresholds identified for each protocol.
  • Grow-and-distil protocols outperform lattice surgery in regimes with limited memory but high entangling rates.
  • Transversal gates are preferred when inter-module gate fidelity is already high.
  • Concrete fidelity and rate targets are given for reaching 10^{-12} logical error rates on superconducting, atomic, and solid-state platforms.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Early modular experiments could test the predicted crossover points by varying connection speed while holding other parameters fixed.
  • The same parameter-mapping approach could be applied to other error-correcting codes to check whether surface-code optima generalize.
  • Hardware teams might use the derived thresholds to decide which interface method to prioritize during prototype development.

Load-bearing premise

Interface performance can be reliably predicted from gate fidelities, entangling rates, and memory resources without large unmodeled errors or platform-specific difficulties.

What would settle it

A physical implementation of one of the analyzed interfaces that reaches the paper's predicted logical error rate when the modeled parameters are met would support the conclusions; a measured error rate significantly higher than predicted would falsify them.

Figures

Figures reproduced from arXiv: 2510.05221 by Frederik K. Marqversen, Gefen Baranes, Johannes Borregaard, Maxim Sirotin.

Figure 1
Figure 1. Figure 1: (a) Distributed algorithm between two nodes, requiring local logical gates (black) as well as distributed logical gates (orange), both with high fidelity. (b) Physical implementation of two nodes, each with a computation zone and a network zone, with physical Bell pairs distributed between both nodes. We are assuming there is a direct quantum connection between qubits in network and computation zones. Thre… view at source ↗
Figure 2
Figure 2. Figure 2: Rate of distributed logical Bell pairs rdistributed as a function of local memory dedicated to distillation. The two x-axes represent the amount of allocated space for distil￾lation in terms of physical qubits (upper) and logical qubits (lower) respectively. Includes rates from both distillation with code growing and distillation without code growing (NG) with a target Bell pair error rate of 10−12. The fi… view at source ↗
Figure 3
Figure 3. Figure 3: Rate of distributed logical Bell pairs rdistributed as a function of physical Bell pair rate rbell. These are given in units of local logical gate rates and physical gate rates respectively. Rates from each of the three methods: Distillation, logical CNOT by lattice surgery, and transver￾sal logical CNOT are included. The figure is for initial physical Bell pair error rate of 1%, a target Bell pair er￾ror … view at source ↗
Figure 4
Figure 4. Figure 4: Logical Bell pair distribution rate rdistributed as a function of networking memory and physical Bell pair rate rbell. The two plots correspond to (top) pbell = 1%, ptarget = 10−12 and (bottom) pbell = 5%, ptarget = 10−6 . Rates are expressed in units of the local physical gate rate rphysical and local syndrome extraction rate rlogical. The y-axes show both physical (right) and logical (left) qubit counts.… view at source ↗
Figure 5
Figure 5. Figure 5: (Left) The two solid lines illustrate the rates produced by the optimal sequences in the limit of low S ′ and high Bell pair rate S ′′. Together, they provide the max￾imal distillation rate for most cases. Only for input rates between CS′ and CS′′ can sequences exist that further im￾prove on these rates. Furthermore, the optimum is known to be restricted to within the gray shaded area. (Right) The distilla… view at source ↗
Figure 6
Figure 6. Figure 6: Schematic of rotated surface code injection and growing from d = 3 to d = 5: (a) corner injection and (b) middle injection. Data qubits enclosed by solid lines are initialised in the |+⟩ state; those with dashed lines are initialised in the |0⟩ state. The purple circle denotes the injection qubit (from a Bell pair). Green and blue represent Z and X stabilisers, respectively. Logical operators ZL and XL are… view at source ↗
Figure 8
Figure 8. Figure 8: Simulated resource-performance map for distributed quantum computing with neutral atoms across three in￾terconnect architectures. The x-axis shows the normalised Bell-pair rate rbell/rphysical, and the y-axis represents the total physical memory required (communication + logic). Colour intensity reflects the achievable logical rate ratio rdistributedlogical/rlocallogical, with distinct regimes highlighting… view at source ↗
read the original abstract

Modular architectures offer a scalable path toward fault-tolerant quantum computing by interconnecting smaller quantum processing units (QPUs) provided that high-rate, fault-tolerant interfaces can be realized across modules. We present a comprehensive analysis and comparison of known and new methods for establishing such interfaces, including lattice surgery, transversal gates, and novel grow-and-distil protocols based on code growing and logical distillation. Using the surface code, we identify optimal interface strategies across a wide range of hardware parameters, such as gate fidelities, entangling rates, and memory resources, and estimate the requirements to achieve logical error rates of $10^{-6}$ and $10^{-12}$. Our results establish when the interface become a bottleneck in the computation and provide guidance for experimental implementations with superconducting, atomic, and solid-state hardware.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript analyzes fault-tolerant interfaces for modular quantum computing architectures. It compares lattice surgery, transversal gates, and novel grow-and-distil protocols based on code growing and logical distillation. Using the surface code, the work sweeps over hardware parameters including gate fidelities, entangling rates, and memory resources to identify optimal interface strategies and estimate requirements for achieving logical error rates of 10^{-6} and 10^{-12}, while determining when interfaces become bottlenecks for superconducting, atomic, and solid-state platforms.

Significance. If the underlying models and simulations hold, the results would provide useful practical guidance for experimental teams by mapping parameter regimes where each interface method is preferable and by highlighting resource thresholds needed for target logical error rates. The explicit comparison across diverse qubit platforms and the introduction of grow-and-distil protocols constitute a concrete contribution to modular architecture design.

major comments (2)
  1. [Methods / Results] The error model for inter-module entangling operations (described in the methods and results sections): the analysis relies on a phenomenological or circuit-level model driven by the listed hardware parameters. Platform-specific correlated noise channels (shared control-line fluctuations in superconducting modules or motional heating in atomic arrays) are not explicitly bounded; if these occur at rates comparable to the modeled entangling errors, the relative overhead and threshold behavior of grow-and-distil versus lattice surgery can shift, directly affecting the reported optimality regions and resource estimates for 10^{-6} and 10^{-12} logical error rates.
  2. [Results] The central claims rest on numerical sweeps that identify optimal strategies; however, the manuscript does not supply sufficient detail on the precise circuit-level error model, simulation parameters, or convergence criteria used to generate the optimality maps. Without these, the quantitative requirements for gate fidelities and entangling rates cannot be independently verified or stress-tested against additional noise sources.
minor comments (2)
  1. [Figures] Figure captions and axis labels should explicitly state the surface-code distance and the precise definition of 'entangling rate' used in each panel to avoid ambiguity when readers compare across protocols.
  2. [Results] A short table summarizing the key hardware-parameter thresholds for each target logical error rate would improve readability and allow quick experimental comparison.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their constructive feedback, which has helped clarify several aspects of our analysis on fault-tolerant interfaces for modular quantum computing. We address each major comment point by point below, indicating revisions where the manuscript will be updated.

read point-by-point responses

  1. Referee: [Methods / Results] The error model for inter-module entangling operations (described in the methods and results sections): the analysis relies on a phenomenological or circuit-level model driven by the listed hardware parameters. Platform-specific correlated noise channels (shared control-line fluctuations in superconducting modules or motional heating in atomic arrays) are not explicitly bounded; if these occur at rates comparable to the modeled entangling errors, the relative overhead and threshold behavior of grow-and-distil versus lattice surgery can shift, directly affecting the reported optimality regions and resource estimates for 10^{-6} and 10^{-12} logical error rates.

    Authors: We agree that our phenomenological error model does not explicitly bound all platform-specific correlated noise sources, which represents a limitation of the current analysis. The model focuses on the dominant parameters (gate fidelities, entangling rates, and memory resources) to enable broad comparisons across superconducting, atomic, and solid-state platforms. In the revised manuscript we will add a new paragraph in the Methods section that discusses these correlated channels, provides order-of-magnitude bounds drawn from recent experimental literature for each platform, and states the assumption that such errors remain at least an order of magnitude below the modeled entangling error rates. We will also note that the reported optimality regions and resource thresholds hold under this assumption and flag the need for more detailed noise modeling in future work. revision: partial

  2. Referee: [Results] The central claims rest on numerical sweeps that identify optimal strategies; however, the manuscript does not supply sufficient detail on the precise circuit-level error model, simulation parameters, or convergence criteria used to generate the optimality maps. Without these, the quantitative requirements for gate fidelities and entangling rates cannot be independently verified or stress-tested against additional noise sources.

    Authors: We thank the referee for highlighting the need for greater reproducibility. The underlying model is a standard circuit-level depolarizing noise model applied to all operations, with error rates set by the hardware parameters listed in Table I. Simulations were performed via Monte Carlo sampling with a minimum of 10^5 shots per data point and convergence defined as the point at which the standard error of the logical error rate drops below 10% of the estimated value. To address the comment we will expand the Methods section with a full description of the error model, the exact simulation parameters, pseudocode for the sweep procedure, and the convergence criteria. We will also make the simulation scripts available as supplementary material with a link in the revised manuscript. revision: yes

Circularity Check

0 steps flagged

No significant circularity; results driven by external hardware parameters and surface-code modeling

full rationale

The paper performs a comparative analysis of interface protocols (lattice surgery, transversal gates, grow-and-distil) under the surface code by sweeping external inputs such as gate fidelities, entangling rates, and memory resources to estimate requirements for target logical error rates of 10^{-6} and 10^{-12}. This constitutes numerical modeling and optimization over independent hardware parameters rather than any self-definitional loop, fitted input renamed as prediction, or load-bearing self-citation that reduces the claimed optimality regions to the paper's own outputs by construction. The derivation chain remains self-contained against external benchmarks and does not exhibit the enumerated circularity patterns.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Only the abstract is available, so the complete set of modeling assumptions cannot be audited. The work appears to rest on standard quantum error correction modeling assumptions for the surface code applied across platforms.

axioms (1)
  • domain assumption Surface code error correction performance can be modeled using gate fidelities, entangling rates, and memory resources as primary inputs across diverse qubit platforms.
    The paper states it uses the surface code for all comparisons and estimates.

pith-pipeline@v0.9.0 · 5668 in / 1261 out tokens · 39236 ms · 2026-05-18T09:04:49.043862+00:00 · methodology

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Forward citations

Cited by 1 Pith paper

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  1. Heterogeneous architectures enable a 138x reduction in physical qubit requirements for fault-tolerant quantum computing under detailed accounting

    quant-ph 2026-04 unverdicted novelty 6.0

    Heterogeneous quantum architectures with task-specific hardware and QEC encodings deliver up to 138x lower physical-qubit overhead than monolithic baselines for fault-tolerant algorithms, including RSA-2048 factoring ...

Reference graph

Works this paper leans on

57 extracted references · 57 canonical work pages · cited by 1 Pith paper · 6 internal anchors

  1. [1]

    Nature598(7879), 137–143 (2021)

    L. Egan et al. “Fault-tolerant control of an error- corrected qubit”. In:Nature598.7880 (Oct. 1, 2021), pp. 281–286.doi:10.1038/s41586-021- 03928-y

    work page doi:10.1038/s41586-021- 2021

  2. [2]

    Logical quantum processor based on reconfigurable atom arrays

    D. Bluvstein et al. “Logical quantum processor based on reconfigurable atom arrays”. In:Na- ture626.7997 (Feb. 1, 2024), pp. 58–65.doi:10. 1038/s41586-023-06927-3

    work page 2024

  3. [3]

    P. S. Rodriguez et al.Experimental Demonstra- tion of Logical Magic State Distillation. 2024. arXiv:2412.15165 [quant-ph]

    work page arXiv 2024

  4. [4]

    B. W. Reichardt et al.Logical computation demonstrated with a neutral atom quantum pro- cessor. 2024. arXiv:2411.11822 [quant-ph]

    work page internal anchor Pith review Pith/arXiv arXiv 2024

  5. [5]

    High-fidelity telepor- tation of a logical qubit using transversal gates and lattice surgery

    C. Ryan-Anderson et al. “High-fidelity telepor- tation of a logical qubit using transversal gates and lattice surgery”. In:Science385.6715 (2024), pp. 1327–1331.doi:10.1126/science.adp6016

    work page doi:10.1126/science.adp6016 2024

  6. [6]

    Benchmarking a trapped-ion quantum computer with 30 qubits

    J.-S. Chen et al. “Benchmarking a trapped-ion quantum computer with 30 qubits”. In:Quantum 8 (Nov. 2024), p. 1516.doi:10.22331/q-2024- 11-07-1516

    work page doi:10.22331/q-2024- 2024

  7. [7]

    Bluvstein, A

    D. Bluvstein et al. “Architectural mechanisms of auniversalfault-tolerantquantumcomputer”.In: arXiv preprint arXiv:2506.20661(2025)

    work page arXiv 2025

  8. [8]

    Lacroix et al.Scaling and logic in the color code on a superconducting quantum processor

    N. Lacroix et al.Scaling and logic in the color code on a superconducting quantum processor

    work page

  9. [9]

    arXiv:2412.14256 [quant-ph]

    work page arXiv

  10. [10]

    Encoding a magic state with beyond break-even fidelity

    R. S. Gupta et al. “Encoding a magic state with beyond break-even fidelity”. In:Nature625.7994 (Jan. 1, 2024), pp. 259–263.doi:10 . 1038 / s41586-023-06846-3

    work page 2024

  11. [11]

    Hardware-efficient quan- tum error correction via concatenated bosonic qubits

    H. Putterman et al. “Hardware-efficient quan- tum error correction via concatenated bosonic qubits”. In:Nature638.8052 (Feb. 1, 2025), pp. 927–934.doi:10.1038/s41586-025-08642- 7

    work page doi:10.1038/s41586-025-08642- 2025

  12. [12]

    Quantum-centric supercom- puting for materials science: A perspective on challenges and future directions

    Y. Alexeev et al. “Quantum-centric supercom- puting for materials science: A perspective on challenges and future directions”. In:Future Gen- eration Computer Systems160 (Nov. 2024), pp. 666–710.doi:10 . 1016 / j . future . 2024 . 04.060

    work page 2024

  13. [13]

    Quantum computational chemistry

    S. McArdle et al. “Quantum computational chemistry”. In:Rev. Mod. Phys.92 (1 Mar. 2020), p. 015003.doi:10 . 1103 / RevModPhys . 92 . 015003

    work page 2020

  14. [14]

    Quantum 5, 433 (2021) https://doi.org/10.22331/q-2021-04-15-433

    C. Gidney and M. Ekerå. “How to factor 2048 bit RSA integers in 8 hours using 20 million noisy qubits”. In:Quantum5 (Apr. 2021), p. 433.doi: 10.22331/q-2021-04-15-433

    work page doi:10.22331/q-2021-04-15-433 2048

  15. [15]

    Even More Efficient Quantum Com- putations of Chemistry Through Tensor Hyper- contraction

    J. Lee et al. “Even More Efficient Quantum Com- putations of Chemistry Through Tensor Hyper- contraction”. In:PRX Quantum2 (3 July 2021), p. 030305.doi:10.1103/PRXQuantum.2.030305

    work page doi:10.1103/prxquantum.2.030305 2021

  16. [16]

    M. E. Beverland et al.Assessing requirements to scale to practical quantum advantage. 2022. arXiv:2211.07629 [quant-ph]

    work page internal anchor Pith review Pith/arXiv arXiv 2022

  17. [17]

    A. M. Dalzell et al.Quantum algorithms: A sur- vey of applications and end-to-end complexities

    work page

  18. [18]

    arXiv:2310.03011 [quant-ph]

    work page arXiv

  19. [19]

    How to factor 2048 bit RSA integers with less than a million noisy qubits

    C. Gidney. “How to factor 2048 bit RSA integers with less than a million noisy qubits”. In:arXiv preprint arXiv:2505.15917(2025)

    work page internal anchor Pith review Pith/arXiv arXiv 2048

  20. [20]

    Physical Review A33(5), 2913–2927 (1986)

    C. Monroe et al. “Large-scale modular quantum- computer architecture with atomic memory and photonic interconnects”. In:Phys. Rev. A89 (2 Feb. 2014), p. 022317.doi:10.1103/PhysRevA. 89.022317

    work page doi:10.1103/physreva 2014

  21. [21]

    Fault-tolerant optical intercon- nects for neutral-atom arrays

    J. Sinclair et al. “Fault-tolerant optical intercon- nects for neutral-atom arrays”. In:Physical Re- view Research7.1 (2025), p. 013313

    work page 2025

  22. [22]

    Stack et al.Assessing Teleportation of Log- ical Qubits in a Distributed Quantum Architec- ture under Error Correction

    J. Stack et al.Assessing Teleportation of Log- ical Qubits in a Distributed Quantum Architec- ture under Error Correction. 2025. arXiv:2504. 05611 [quant-ph]

    work page 2025

  23. [23]

    Fault-tolerant connection of error-corrected qubits with noisy links,

    J. Ramette et al. “Fault-tolerant connection of error-corrected qubits with noisy links”. en. In: npj Quantum Information10.1 (June 2024). Publisher: Nature Publishing Group, pp. 1–6. doi:10.1038/s41534-024-00855-4

    work page doi:10.1038/s41534-024-00855-4 2024

  24. [24]

    C. A. Pattison et al.Fast quantum interconnects via constant-rate entanglement distillation. en. arXiv:2408.15936 [quant-ph]. Aug. 2024

    work page arXiv 2024

  25. [25]

    A magic state’s fidelity can be superior to the oper- ations that created it

    Y. Li. “A magic state’s fidelity can be superior to the operations that created it”. en. In:New Journal of Physics17.2 (Feb. 2015), p. 023037. doi:10.1088/1367-2630/17/2/023037

    work page doi:10.1088/1367-2630/17/2/023037 2015

  26. [26]

    Surface codes: Towards practical large-scale quantum computation

    A. G. Fowler et al. “Surface codes: Towards practical large-scale quantum computation”. In: Physical Review A—Atomic, Molecular, and Op- tical Physics86.3 (2012), p. 032324

    work page 2012

  27. [27]

    Majidy et al.Building Quantum Computers: A Practical Introduction

    S. Majidy et al.Building Quantum Computers: A Practical Introduction. Cambridge University Press, 2024

    work page 2024

  28. [28]

    Quantum error correction below the surface code threshold

    R. Acharya et al. “Quantum error correction below the surface code threshold”. In:Nature 638.8052 (2025), pp. 920–926.doi:10 . 1038 / s41586-024-08449-y. 10

    work page 2025

  29. [29]

    Universal high-fidelity quan- tum gates for spin-qubits in diamond

    H. Bartling et al. “Universal high-fidelity quan- tum gates for spin-qubits in diamond”. In:arXiv preprint arXiv:2403.10633(2024)

    work page arXiv 2024

  30. [30]

    Entanglement of nanophotonic quantum memory nodes in a telecom network,

    C. M. Knaut et al. “Entanglement of nanopho- tonic quantum memory nodes in a telecom net- work”. In:Nature629.8012 (May 2024), pp. 573– 578.doi:10.1038/s41586-024-07252-z

    work page doi:10.1038/s41586-024-07252-z 2024

  31. [31]

    Algorithmic fault tolerance for fast quantum computing

    H. Zhou et al.Algorithmic Fault Tolerance for Fast Quantum Computing. en. arXiv:2406.17653 [quant-ph]. June 2024

    work page arXiv 2024

  32. [32]

    Correlated Decoding of Logical Algorithms with Transversal Gates

    M. Cain et al. “Correlated Decoding of Logical Algorithms with Transversal Gates”. In:Physi- cal Review Letters133.24 (Dec. 2024). Publisher: American Physical Society, p. 240602.doi:10. 1103/PhysRevLett.133.240602

    work page 2024

  33. [33]

    Logical quantum processor based on reconfigurable atom arrays

    D. Bluvstein et al. “Logical quantum processor based on reconfigurable atom arrays”. In:Na- ture626.7997 (2024), pp. 58–65.doi:10.1038/ s41586-023-06927-3

    work page 2024

  34. [34]

    A tweezer array with 6100 highly coherent atomic qubits

    H. J. Manetsch et al. “A tweezer array with 6100 highlycoherentatomicqubits”.In:arXiv preprint arXiv:2403.12021(2024)

    work page internal anchor Pith review arXiv 2024

  35. [35]

    Continuous operation of a co- herent 3,000-qubit system

    N.-C. Chiu et al. “Continuous operation of a co- herent 3,000-qubit system”. In:arXiv preprint arXiv:2506.20660(2025)

    work page internal anchor Pith review arXiv 2025

  36. [36]

    Robust multi-qubit quantum network node with integrated error detection

    P.-J. Stas et al. “Robust multi-qubit quantum network node with integrated error detection”. In:Science378.6619 (2022), pp. 557–560

    work page 2022

  37. [37]

    Universal distributed blind quantum computing with solid-state qubits

    Y.-C. Wei et al. “Universal distributed blind quantum computing with solid-state qubits”. In: Science388.6746 (2025), pp. 509–513.doi:10. 1126/science.adu6894

    work page 2025

  38. [38]

    Designing Fault-Tolerant Blind Quantum Computation

    G. Baranes et al. “Designing Fault-Tolerant Blind Quantum Computation”. In:arXiv preprint arXiv:2505.21621(2025)

    work page arXiv 2025

  39. [39]

    Suppressing quantum errors by scaling a surface code logical qubit

    R. Acharya et al. “Suppressing quantum errors by scaling a surface code logical qubit”. In:Na- ture614.7949 (Feb. 2023), pp. 676–681.doi:10. 1038/s41586-022-05434-1

    work page 2023

  40. [40]

    Loophole-free Bell inequality vio- lation with superconducting circuits

    S. Storz et al. “Loophole-free Bell inequality vio- lation with superconducting circuits”. In:Nature 617.7960 (2023), pp. 265–270.doi:10 . 1038 / s41586-023-05885-0

    work page 2023

  41. [41]

    et al., Leveraging Atom Loss Errors in Fault Tolerant Quantum Algorithms, arXiv (2025), 2502.20558 [quant-ph]

    G. Baranes et al. “Leveraging atom loss errors in fault tolerant quantum algorithms”. In:arXiv preprint arXiv:2502.20558(2025)

    work page arXiv 2025

  42. [42]

    J. P. B. Ataides et al.Constant-Overhead Fault- Tolerant Bell-Pair Distillation using High-Rate Codes. 2025. arXiv:2502.09542 [quant-ph]

    work page arXiv 2025

  43. [43]

    T. J. Yoder et al.Tour de gross: A modular quan- tum computer based on bivariate bicycle codes

    work page

  44. [44]

    arXiv:2506.03094 [quant-ph]

    work page internal anchor Pith review Pith/arXiv arXiv

  45. [45]

    F. K. Marqversen.quantum_computations. https : / / github . com / frederik - kofoed - marqversen / quantum _ computations. original- date: 2024-08-29. Mar. 2025

    work page 2024

  46. [46]

    Sirotin.Growing_simulation.https : / / github

    M. Sirotin.Growing_simulation.https : / / github . com / MaximSirotin / BellPairsCode. original-date: 2025-07-07. July 2025

    work page 2025

  47. [47]

    Magic state injection on the rotated surface code

    L. Lao and B. Criger. “Magic state injection on the rotated surface code”. en. In:Proceedings of the 19th ACM International Conference on Com- puting Frontiers. Turin Italy: ACM, May 2022, pp. 113–120.doi:10.1145/3528416.3530237

    work page doi:10.1145/3528416.3530237 2022

  48. [48]

    Stim: a fast stabilizer circuit simula- tor

    C. Gidney. “Stim: a fast stabilizer circuit simula- tor”. In:Quantum5 (2021), p. 497

    work page 2021

  49. [49]

    Towards Quantum Repeater Nodes with Weakly-Coupled Nuclear Spins in Diamond

    Y. Q. Huan et al. “Towards Quantum Repeater Nodes with Weakly-Coupled Nuclear Spins in Diamond”. In:Quantum 2.0. Optica Publishing Group. 2025, QW4A–3

    work page 2025

  50. [50]

    Physical Review Letters 85(10), 2200–2203 (2000)

    S. Krastanov et al. “Optically Heralded Entan- glement of Superconducting Systems in Quan- tum Networks”. In:Phys. Rev. Lett.127 (4 July 2021), p. 040503.doi:10.1103/PhysRevLett. 127.040503

    work page doi:10.1103/physrevlett 2021

  51. [51]

    Fast correlated decoding of transversal log- ical algorithms

    M. Cain et al.Fast correlated decoding of transversal logical algorithms. arXiv:2505.13587 [quant-ph]. May 2025.doi:10 . 48550 / arXiv . 2505.13587

    work page arXiv 2025

  52. [52]

    Quantum error correction below the surface code threshold

    R. Acharya et al. “Quantum error correction below the surface code threshold”. In:Nature (2024)

    work page 2024

  53. [53]

    Violating Bell’s inequality with remotely connected superconducting qubits

    Y. Zhong et al. “Violating Bell’s inequality with remotely connected superconducting qubits”. In: Nature Physics15.8 (2019), pp. 741–744

    work page 2019

  54. [54]

    Quantum networks with neu- tral atom processing nodes

    J. P. Covey et al. “Quantum networks with neu- tral atom processing nodes”. In:npj Quantum Information9.1 (2023), p. 90.doi:10 . 1038 / s41534-023-00759-9

    work page 2023

  55. [55]

    High-fidelity parallel entan- gling gates on a neutral-atom quantum com- puter

    S. J. Evered et al. “High-fidelity parallel entan- gling gates on a neutral-atom quantum com- puter”. In:Nature622.7982 (2023), pp. 268–272. doi:10.1038/s41586-023-06481-y

    work page doi:10.1038/s41586-023-06481-y 2023

  56. [56]

    An elementary quantum network of single atoms in optical cavities

    S. Ritter et al. “An elementary quantum network of single atoms in optical cavities”. In:Nature 484.7393 (2012), pp. 195–200

    work page 2012

  57. [57]

    High-Rate and High- Fidelity Modular Interconnects between Neutral Atom Quantum Processors

    Y. Li and J. D. Thompson. “High-Rate and High- Fidelity Modular Interconnects between Neutral Atom Quantum Processors”. In:PRX Quantum 5 (2 June 2024), p. 020363.doi:10 . 1103 / PRXQuantum.5.020363. 11 A Balanced pipeline for entan- glement distillation Here we derive the formulae needed for computing the distillation rate of a given distillation sequence...

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