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arxiv: 2604.20482 · v1 · submitted 2026-04-22 · 🪐 quant-ph · cond-mat.mes-hall· physics.ins-det

Valley-Aware Optimal Control of Spin Shuttling Using Cryogenic Integrated Electronics

Pau Dietz Romero , Nermine Chaabani , Lammert Duipmans , Alessandro David , Felix Motzoi , Stefan van Waasen , Lotte Geck This is my paper

Pith reviewed 2026-05-09 23:58 UTC · model grok-4.3

classification 🪐 quant-ph cond-mat.mes-hallphysics.ins-det
keywords spin shuttlingvalley splittingSi/SiGe qubitscryogenic electronicsvelocity modulationoptimal controlquantum dot transportfidelity optimization
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The pith

Valley-aware optimization of cryogenic on-chip waveforms achieves 99.99% average fidelity for shuttling spins over 10 micrometers at 20 m/s.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops an end-to-end co-simulation framework that merges spatially varying valley maps with detailed cryogenic transistor simulations including noise. It introduces a compact integrated signal generator that produces velocity-modulation waveforms by selecting among four discrete resistor settings per shuttling period, with those settings stored in on-chip memory. A noise-aware optimizer tunes only these implementable controls to counteract valley-induced spin mixing. The resulting sequences deliver the reported high fidelity and low power across many simulated disorder realizations. This demonstrates that on-chip storage and replay of optimized controls offers a practical route to reliable long-range spin transport in Si/SiGe devices.

Core claim

An end-to-end co-simulation framework that combines disorder-informed valley maps with transistor-level cryogenic circuit simulations, together with a fully integrated cryogenic shuttling-signal generator that uses discrete circuit settings stored in on-chip memory and a noise-aware optimization procedure that tunes only those implementable controls, produces velocity-modulation waveforms that achieve an average shuttling fidelity of 99.99 ± 0.007% at 20 m/s over 10 μm while consuming tens of μW during transport across simulated valley and noise realizations.

What carries the argument

The noise-aware optimization procedure that tunes only four discrete resistor settings per period to generate valley-compensating velocity-modulation waveforms within the co-simulation framework.

Load-bearing premise

The co-simulation framework accurately captures real-world valley disorder and electronic noise effects in Si/SiGe devices so that the discrete circuit settings can be implemented without additional unmodeled effects.

What would settle it

Experimental measurement of actual shuttling fidelity in a fabricated Si/SiGe device driven by the cryogenic circuit outputting the optimized waveforms, compared against the simulated 99.99% average.

Figures

Figures reproduced from arXiv: 2604.20482 by Alessandro David, Felix Motzoi, Lammert Duipmans, Lotte Geck, Nermine Chaabani, Pau Dietz Romero, Stefan van Waasen.

Figure 1
Figure 1. Figure 1: FIG. 1. End-to-end co-simulation workflow used to optimize and validate shuttling operations. The cryogenic signal generator is [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. Schematic of the integrated cryogenic shuttling sig [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Schematic of the programmable RC network driving [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Analytical waveforms illustrating the effect of dis [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. Noise-induced purity dispersion at an average shut [PITH_FULL_IMAGE:figures/full_fig_p008_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. Influence of the average shuttling velocity [PITH_FULL_IMAGE:figures/full_fig_p008_6.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. Shuttling error 1 [PITH_FULL_IMAGE:figures/full_fig_p009_8.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. Benchmark of hardware-embedded shuttling control [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9. Simplified layout of a single shuttling-signal phase [PITH_FULL_IMAGE:figures/full_fig_p012_9.png] view at source ↗
Figure 11
Figure 11. Figure 11: FIG. 11. Standard deviation of the final spin purity, [PITH_FULL_IMAGE:figures/full_fig_p014_11.png] view at source ↗
read the original abstract

Electron shuttling is emerging as a key mechanism for enabling long-range coupling in scalable spin-qubit architectures. Bringing shuttling waveform generation into the cryostat can improve scalability, but imposes strict area and power constraints on the control electronics. Concurrently, shuttling in Si/SiGe is further limited by a spatially varying valley splitting that induces spin--valley mixing and degrades coherence. Here, we make three contributions that address these limitations jointly: (i) an end-to-end co-simulation framework that combines disorder-informed valley maps with transistor-level cryogenic circuit simulations including electronic noise; (ii) a fully integrated cryogenic shuttling-signal generator tailored to velocity modulation, enabling period-wise waveform shaping through discrete circuit settings stored in on-chip memory; and (iii) a noise-aware optimization procedure that tunes only these implementable circuit controls, using one of four discrete resistor settings per period, to generate high-fidelity shuttling sequences. Across simulated valley and noise realizations in our co-simulation framework, the optimized velocity-modulation waveforms improve transport performance, achieving an average shuttling fidelity of $99.99 \pm 0.007\%$ at $v_{\mathrm{avg}} = 20~\mathrm{m\,s^{-1}}$ over a distance of $10~\mu\mathrm{m}$, while maintaining active analog power consumption in the tens of $\mu\mathrm{W}$ during shuttling. This validates on-chip storage and replay of optimized control settings as a practical strategy to mitigate valley disorder in scalable shuttling architectures.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

0 major / 4 minor

Summary. The manuscript presents an end-to-end co-simulation framework that integrates spatially varying valley splitting maps for Si/SiGe with transistor-level cryogenic noise models. It describes a fully integrated cryogenic circuit for generating velocity-modulation shuttling waveforms via discrete resistor settings (one of four per period) stored in on-chip memory, together with a noise-aware optimization that tunes only these implementable controls. Simulations across multiple valley and noise realizations report an average shuttling fidelity of 99.99 ± 0.007% at 20 m s^{-1} over 10 μm while keeping active analog power in the tens of μW.

Significance. If the co-simulation framework is representative, the work shows that on-chip replay of optimized discrete control settings can mitigate valley-disorder effects in shuttling while satisfying cryogenic power and area limits. The restriction of the optimizer to physically realizable parameters and the use of multi-realization simulations are concrete strengths that support practical scalability claims for spin-qubit architectures.

minor comments (4)
  1. Abstract: the reported uncertainty (±0.007%) should be explicitly defined (standard deviation across realizations, standard error, etc.) and the number of realizations used should be stated.
  2. Abstract: the phrase 'tens of μW' is imprecise; a specific average or range obtained from the circuit simulations would improve quantitative clarity.
  3. The manuscript would benefit from a concise description or pseudocode of the optimization procedure (objective function, constraints, and convergence criteria) to make the noise-aware tuning reproducible from the text alone.
  4. Figure or table captions that present fidelity versus velocity or power should include error bars or shaded regions corresponding to the reported variation over realizations.

Simulated Author's Rebuttal

0 responses · 0 unresolved

We thank the referee for their positive assessment of the manuscript, the recognition of its practical strengths in co-simulation and noise-aware optimization, and the recommendation for minor revision. We have prepared revisions accordingly.

Circularity Check

0 steps flagged

No significant circularity detected

full rationale

The paper describes an end-to-end co-simulation framework that integrates external valley-disorder maps with transistor-level cryogenic noise models, followed by an optimization that tunes only four discrete, implementable resistor settings per shuttling period. The reported average fidelity of 99.99 ± 0.007% is obtained by direct numerical evaluation inside this framework; it is not obtained by re-expressing the fitted controls as a prediction of themselves, nor by any self-definitional identity, ansatz smuggled via citation, or load-bearing self-citation chain. The derivation chain therefore remains self-contained against the stated external models and does not reduce to its own inputs by construction.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The central claim rests on standard models of quantum dots and circuits, with the optimization introducing constrained discrete parameters rather than new free ones or entities.

free parameters (1)
  • discrete resistor settings per period
    Four discrete resistor settings are selected by the optimizer but constrained to implementable circuit values.
axioms (1)
  • domain assumption Valley splitting varies spatially according to disorder-informed maps.
    Used to generate the valley maps for co-simulation of spin-valley mixing.

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Reference graph

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