Paper Citation Record · LEDGER

OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

As of 18 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 21 inbound Pith citation observations for arXiv:2407.16237.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2407.16237 v2

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 21 of 21 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-18T06:34:40.430872+00:00

measured 21 of 21 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-16T11:50:20.307922Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-03T00:47:30.472098Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation bc5c1f02-568c-4d9c-a0d8-1a356e3e14ee · inbound

MAGE: A Multi-Agent Engine for Automated RTL Code Generation cites this paper.

MAGE: A Multi-Agent Engine for Automated RTL Code Generation OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-11T18:27:06.408068Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 65a50014-beea-4df7-804b-0aec962c85b6 · inbound

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency cites this paper.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:06.931196Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 159f1594-bdb5-4bf3-86e4-5cc13f546e29 · inbound

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model cites this paper.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.307922Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation eb35afca-3a91-472e-949a-1986f0aaa904 · inbound

VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation cites this paper.

VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-16T11:25:20.155548Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d6ba3cc4-d250-4185-8ac9-fb223539d838 · inbound

Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback cites this paper.

Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-16T11:22:02.276316Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1ffe184e-cef1-4348-a5bc-ed7966828962 · inbound

Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs cites this paper.

Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 34

Resolution: unresolved; no resolver link, observed 2026-08-15T22:51:43.776823Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 98c79d38-bc6e-4606-8756-18247cb13ca8 · inbound

RTL++: Graph-enhanced LLM for RTL Code Generation cites this paper.

RTL++: Graph-enhanced LLM for RTL Code Generation OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-15T22:36:25.090851Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3efcbdcb-afbf-44a1-ab11-7a8721a2fad5 · inbound

Generalizing Large Language Model Usability Across Resource-Constrained cites this paper.

Generalizing Large Language Model Usability Across Resource-Constrained OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-15T22:08:53.132727Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2adf91ac-1580-440e-a6f3-f8cef7d456db · inbound

DeepRTL2: A Versatile Model for RTL-Related Tasks cites this paper.

DeepRTL2: A Versatile Model for RTL-Related Tasks OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-07T13:18:30.797035Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 54b1ee55-1bf2-47a1-b874-da1be65568ec · inbound

DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs cites this paper.

DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-06T20:40:15.769229Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9e362083-ce54-4acd-aa56-229f907c4f96 · inbound

Iceberg: Enhancing HLS Modeling with Synthetic Data cites this paper.

Iceberg: Enhancing HLS Modeling with Synthetic Data OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-06T17:51:02.605641Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 72125041-3c31-41d1-a061-b7525c0e3a05 · inbound

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation cites this paper.

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-06T18:54:02.176953Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f770b0c3-672a-47a9-a917-7c635ec85a49 · inbound

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code cites this paper.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:13.447783Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a855a0da-2a61-4568-937b-73c76b8111ad · inbound

VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation cites this paper.

VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 11

Resolution: verified exact; arxiv_id, observed 2026-05-11T12:11:07.019732Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation b766bd0e-9a23-4b22-a50c-0337ecdfb65f · inbound

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog cites this paper.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 16

Resolution: verified exact; arxiv_id, observed 2026-05-11T21:31:14.694367Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 3f6cf228-2bf7-4a5f-b78c-14a48724eae3 · inbound

RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision cites this paper.

RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 4

Resolution: verified exact; arxiv_id, observed 2026-05-19T14:42:37.339392Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 7a084711-70e0-490c-9bd8-9c1771211f98 · inbound

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation cites this paper.

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 23

Resolution: verified exact; arxiv_id, observed 2026-06-29T18:53:51.317118Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 410e0030-61a3-48a2-a577-99bd6768ea01 · inbound

ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards cites this paper.

ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 9

Resolution: verified exact; arxiv_id, observed 2026-07-02T20:27:22.720643Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation af2e4d1d-20ba-4eb4-93d0-5a535df2a2f2 · inbound

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models cites this paper.

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 7

Resolution: verified exact; arxiv_id, observed 2026-07-03T00:47:30.473866Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 3470f79e-ec5a-465f-8980-49a2b7b61cdb · inbound

Agentic Hardware Design as Repository-Level Code Evolution cites this paper.

Agentic Hardware Design as Repository-Level Code Evolution OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 12

Resolution: verified exact; arxiv_id, observed 2026-07-01T18:45:58.306268Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 3ee96091-829c-4fc1-914e-68825b615722 · inbound

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation cites this paper.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:16.727289Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.