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arxiv: 2604.09796 · v2 · pith:STPTC473new · submitted 2026-04-10 · 🪐 quant-ph · physics.app-ph

Resist-free shadow deposition using silicon trenches for Josephson junctions in superconducting qubits

Tathagata Banerjee , Stephen Daniel Funni , Saswata Roy , Judy J. Cha , Valla Fatemi This is my paper

Pith reviewed 2026-05-19 18:08 UTC · model grok-4.3

classification 🪐 quant-ph physics.app-ph
keywords Josephson junction fabricationsuperconducting qubitsresist-free depositionsilicon trenchesshadow evaporationqubit coherencequantum device fabrication
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The pith

Resist-free shadow deposition with silicon trenches fabricates Josephson junctions achieving 184 microsecond relaxation times.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper demonstrates a fabrication method for Josephson junctions in superconducting qubits that avoids polymer resists by using etched silicon trenches for shadowing during metal deposition. This approach reduces chemical contamination at interfaces and allows better surface preparation. It achieves median energy relaxation times of 184 microseconds in fabricated qubits. The method is presented as CMOS-compatible and scalable for integration with other qubit fabrication advances.

Core claim

The central discovery is a resist-free method for fabricating Al-AlOx-Al Josephson junctions using shadow deposition in silicon trenches. This technique eliminates the need for polymer masks, thereby minimizing contamination and expanding options for substrate cleaning and material choices. Qubits made this way exhibit energy relaxation times with a median of 184 microseconds and stable fluctuations over 35 hours.

What carries the argument

Etched silicon trenches that serve as shadow masks to define the junction areas during aluminum and aluminum oxide deposition without using resist polymers.

If this is right

  • The approach integrates easily with existing innovations in base layer fabrication and chemical processing.
  • It widens the process window for substrate preparation and introduction of new materials platforms.
  • Energy relaxation fluctuations remain narrow and normally distributed on a 35-hour timescale.
  • Minimal contamination occurs at the substrate-metal interface compared to resist-based methods.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • This method may enable the use of junction materials or surface treatments previously incompatible with polymer resists.
  • Improved scalability could support larger qubit arrays with consistent performance.
  • Integration with CMOS processes might accelerate the development of hybrid quantum-classical chips.

Load-bearing premise

The silicon trench geometry reliably creates the necessary shadowing for clean junction formation without adding defects or limiting scalability.

What would settle it

A direct comparison showing that qubits made with this trench method have significantly lower energy relaxation times or higher interface contamination than those made with standard resist methods would challenge the central claim.

Figures

Figures reproduced from arXiv: 2604.09796 by Judy J. Cha, Saswata Roy, Stephen Daniel Funni, Tathagata Banerjee, Valla Fatemi.

Figure 1
Figure 1. Figure 1: FIG. 1. Josephson junction fabrication process. (a) Dolan-bridge junction fabrication: a wafer is coated with double layer [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. STEM/EELS. (a) Virtual annular dark field image [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Qubit fabrication. (a) Full qubit fabrication process. The evaporated junction film is coated in photoresist, followed [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Qubit measurement data. (a), (b) Representative [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. T [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
read the original abstract

Superconducting qubit fabrication innovations continue to be explored to achieve higher performance. Despite improvements to base layer fabrication and processing, resist-based Josephson junction (JJ) schemes have largely remained unchanged. The polymer mask during deposition causes chemical contamination and limits in situ and ex situ surface preparation, junction materials, and scalability. Here, we demonstrate a resist-free approach to junction fabrication based on etched silicon trenches that is CMOS compatible and easily integrated into existing innovations in qubit base layer fabrication and chemical processing. We fabricate Al-AlOx-Al JJs and qubits using this method, measuring median energy relaxation times up to 184 microseconds. We find minimal contamination at the substrate-metal interface and fluctuations of energy relaxation on a 35 hour timescale that are narrow and normally distributed. The method widens the process window for substrate preparation and new materials platforms.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript introduces a resist-free shadow deposition technique for fabricating Josephson junctions (JJs) in superconducting qubits using etched silicon trenches. This method aims to avoid chemical contamination from polymer resists, enabling better surface preparation and CMOS compatibility. The authors fabricate Al-AlOx-Al JJs and qubits, reporting a median energy relaxation time (T1) of up to 184 microseconds, minimal contamination at the substrate-metal interface, and narrow, normally distributed T1 fluctuations over a 35-hour period. The approach is claimed to widen the process window for substrate preparation and new materials platforms.

Significance. If the central claims hold, this fabrication innovation could meaningfully advance superconducting qubit technology by mitigating resist-induced contamination and enabling broader substrate and material choices. The reported T1 performance and process integration potential position it as a practical step toward scalable, higher-coherence devices.

major comments (2)
  1. The assertion that silicon trench shadowing delivers reliable, resist-free junction formation equivalent to or better than polymer masks is load-bearing for the CMOS-compatibility and easy-integration claims. However, the manuscript provides no quantitative metrics on critical-current spread, junction-area uniformity (e.g., from SEM/AFM), or direct IcRn comparisons to resist-based controls fabricated in the same run. Without these data it remains possible that the observed T1 values arise from substrate preparation improvements rather than the trench geometry itself.
  2. Abstract and results sections: the median T1 of 184 μs and narrow 35-hour fluctuations are presented without full datasets, error bars, or statistical details on device-to-device variation. This information is required to substantiate the reproducibility and reliability assertions that underpin the method's claimed advantages.
minor comments (2)
  1. Figures showing trench profiles and deposited junctions should include explicit scale bars, aspect-ratio values, and deposition-angle annotations to allow independent assessment of shadowing consistency.
  2. The discussion of 'minimal contamination at the substrate-metal interface' would be strengthened by specifying the characterization technique (e.g., XPS, TEM) and providing representative spectra or images.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their insightful comments on our manuscript. We address each of the major comments in detail below and have revised the manuscript to incorporate additional data and clarifications where possible.

read point-by-point responses

  1. Referee: The assertion that silicon trench shadowing delivers reliable, resist-free junction formation equivalent to or better than polymer masks is load-bearing for the CMOS-compatibility and easy-integration claims. However, the manuscript provides no quantitative metrics on critical-current spread, junction-area uniformity (e.g., from SEM/AFM), or direct IcRn comparisons to resist-based controls fabricated in the same run. Without these data it remains possible that the observed T1 values arise from substrate preparation improvements rather than the trench geometry itself.

    Authors: We agree that quantitative metrics on critical current spread and junction uniformity would provide stronger evidence for the equivalence or superiority of the trench-based method. The current manuscript emphasizes the resulting qubit performance metrics, including the high median T1 and minimal contamination, as the key indicators of successful junction formation. To address this, we have added SEM and AFM data showing junction area uniformity in the revised manuscript. Direct IcRn comparisons to resist-based controls were not included in this study as the focus was on demonstrating the new process; however, we plan to include such comparisons in future work. The CMOS compatibility stems from the use of standard silicon etching techniques rather than solely from the junction performance. revision: partial

  2. Referee: Abstract and results sections: the median T1 of 184 μs and narrow 35-hour fluctuations are presented without full datasets, error bars, or statistical details on device-to-device variation. This information is required to substantiate the reproducibility and reliability assertions that underpin the method's claimed advantages.

    Authors: We appreciate this feedback. The manuscript reports the median T1 and the nature of fluctuations, but to enhance clarity and substantiate the claims, we have expanded the results section to include the full dataset of measured T1 values, associated error bars, and statistical analysis of device-to-device variation. The 35-hour fluctuations are shown to follow a normal distribution, and we have added details on the number of devices measured and the standard deviation. revision: yes

Circularity Check

0 steps flagged

No circularity: purely experimental fabrication and measurement results

full rationale

The manuscript presents a fabrication process for Al-AlOx-Al Josephson junctions using etched silicon trenches, followed by direct experimental measurements of qubit energy relaxation times (median T1 up to 184 µs) and interface contamination. No equations, theoretical derivations, fitted parameters, or predictions appear in the provided text or abstract. Claims rest on empirical device performance data rather than any self-referential chain, self-citation load-bearing premise, or ansatz. The work is self-contained against external benchmarks with no reduction of outputs to inputs by construction.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The work rests on standard assumptions of superconducting thin-film deposition and qubit measurement rather than new free parameters or invented entities; no ad-hoc constants are introduced to support the central performance claims.

axioms (1)
  • domain assumption Standard assumptions in thin-film deposition and superconducting qubit characterization hold for the new trench geometry.
    Invoked when claiming CMOS compatibility and integration with existing base-layer processes.

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