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Stitched surface codes: planar concatenation through GHZ corridors

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Mohamed A. Shalby, Alexandre Bourassa, Amir Karamlou, Leigh Martin, Alexis Morvan, Nicholas Noll, Craig Gidney, Leonid P. Pryadko

Quantum Physics · Submitted 15 Oct 2026 · 56 references

Pith's verdict: A well-executed, transparent concatenated surface-code architecture with honest limitations; the circuit-distance saturation bound for t>7 remains unverified but the authors flag it.

T0 · AI review

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arXiv ID2610.21357 (version 1)
Pith IDYT2Y5C3Y, Pith's permanent record of this paper and its review
CitationAlexandre Bourassa, Alexis Morvan, Amir Karamlou, Craig Gidney, Leigh Martin, Leonid P. Pryadko, Mohamed A. Shalby, Nicholas Noll. "Stitched surface codes: planar concatenation through GHZ corridors." arXiv:2610.21357 (2026). https://pith.science/paper/YT2Y5C3Y
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The paper

The paper claims

Stitched surface codes achieve distance-2t protection by measuring the [[4,2,2]] outer code through GHZ corridors on a square lattice with nearest-neighbor connectivity.

The reading

This paper introduces an architecture that concatenates four rotated surface-code patches with the [[4,2,2]] outer detection code using narrow GHZ ancilla corridors that run between the patches. The design preserves nearest-neighbor connectivity on a square lattice and encodes two logical qubits at code distance 2t, twice the patch distance t. The outer-code stabilizers are measured by verified GHZ states prepared and read out in situ, and all fault mechanisms are engineered to be graphlike so that the full syndrome is decoded by a single minimum-weight perfect matching pass. Circuit simulations show logical error rates scaling as p^t, consistent with distance-2t protection. Experiments on a 105-qubit Willow processor demonstrate a reduction in logical error rate from d=4 to d=6, confirming that the architecture works on current hardware.

What carries the argument

The key mechanism is the GHZ corridor: a line of 4t ancilla qubits that runs between the four surface-code patches, prepared in a Greenberger–Horne–Zeilinger (GHZ) state using a constant-depth measurement-based protocol. After r_v rounds of verification that detect preparation errors, the GHZ ancilla interacts transversally with the data qubits of the patches to read out the weight-4t outer-code stabilizer generators XXXX and ZZZZ. The corridor qubits also serve as boundary stabilizer ancillae for the patches, enabling dual use that keeps the total overhead to 8t+1 qubits.

Extended reading notes

Core claim

The central discovery is that concatenating four rotated surface-code patches with the [[4,2,2]] outer code, and measuring the two weight-4t outer stabilizers via GHZ ancilla states prepared on narrow corridors between the patches, yields a [[$4t^{2}$, 2, 2t]] code on a square lattice with nearest-neighbor gates. The corridor circuit includes a constant-depth GHZ preparation followed by r_v verification rounds, and all hyperedge fault mechanisms that arise are decomposed into graphlike components, so the complete detector error model is solvable by minimum-weight perfect matching. The design achieves circuit distance d_circ = min(2t, r_v+3) and, in both simulation and hardware, the logical error rate scales as p^t, confirming that the concatenated code functions as a distance-2t fault-tolerant memory.

Load-bearing premise

The paper assumes that the circuit distance d_circ = min(2t, r_v+3) holds for all t, but this expression is verified exactly only for t up to 7 using exhaustive search; for larger t, Stim's graphlike search only provides an upper bound, so the distance scaling for t>7 depends on unverified bounds.

Editorial extensions

If this is right

  • At equal code distance, the stitched layout uses fewer qubits than two independent surface-code patches once the physical error rate is below a crossover value, asymptotically halving the qubit count per logical qubit.
  • The architecture provides a near-term testbed for concatenated quantum error correction, since it operates on a square lattice with nearest-neighbor gates and has been demonstrated on a 105-qubit processor.
  • The GHZ corridor method for measuring weight-4t stabilizers without lattice surgery or long-range gates can be adapted to other small outer codes whose stabilizers can be routed through planar corridors.
  • The design ensures that all fault mechanisms are graphlike, so decoding can be done with a single pass of minimum-weight perfect matching (with optional correlated reweighting), avoiding the need for slower hyperedge-capable decoders.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The slow accumulation of time-like distance in the outer-code extraction (one unit of time-like distance requires 2(r_v+1) surface-code cycles) suggests that GHZ-corridor-based concatenation is well suited for long-term memory but not for fast logical operations; logical gates should instead use patch boundaries or code automorphisms.
  • The experimental demonstration on a Willow processor, despite using qubits not optimized for repeated measurement and reset, shows that the corridor overhead is manageable on current superconducting devices, opening the possibility of exploring other concatenated architectures with similar planar layouts.
  • The verification-depth tradeoff reveals a general design principle: for concatenated codes with large-weight stabilizers, the number of verification rounds can be tuned to match the physical error rate, optimizing the balance between hook-error suppression and round duration.
Original abstract

We present a fault-tolerant quantum-memory architecture that concatenates four distance-t rotated surface-code patches with the [[4,2,2]] outer code, encoding two logical qubits at code distance d = 2t in a physical footprint of N < 2(2t+1)^2 qubits on a square lattice with nearest-neighbor connectivity. The outer-code stabilizer generators XXXX and ZZZZ, each of physical weight 4t, are measured in situ via verified Greenberger-Horne-Zeilinger (GHZ) ancillae distributed through narrow corridors between adjacent patches, without lattice surgery or long-range gates. The outer-code gadgets introduce hyperedge fault mechanisms, but by design each decomposes into graphlike components, so the complete syndrome is decoded by a single minimum-weight-perfect-matching pass. Circuit-level simulations show logical error rates that scale as p^t, consistent with distance-2t protection. Finally, we implement the construction experimentally on a 105-qubit Willow superconducting processor in both the ZZ and XX memory bases. With the correlated-matching decoder, increasing the code distance from d = 4 to d = 6 reduces the block logical error rate by a factor of 1.52. The construction thus provides a near-term testbed for concatenated architectures beyond the standard surface code.

The compiled record

The paper's own sentences, arranged, kept beside the review and separate from it. Each label is drawn from a closed vocabulary; the number beside it is the probability the classifier gave that label. Numbers in the tables are the authors', checked by code. No sentence in this record was written by a model.

Compiled by classifier-1.13.0 via TypeSafe API, question bank abstract-p1-20260923, 2026-10-16: 1 request, 5,822 input tokens.

What the abstract itself states, as probabilities: claims first 0.06 · states limitation 0.45 · human participants 0.02 · controlled comparison 0.14 · randomized assignment 0.01 · states quantitative result 0.98 · compares with prior results 0.25 · mentions code or data availability 0.03.

The abstract, sentence by sentence

arXiv listing abstract v1. Results and the main claim are underlined; .

We present a fault-tolerant quantum-memory architecture that concatenates four distance-t rotated surface-code patches with the [[4,2,2]] outer code, encoding two logical qubits at code distance d = 2t in a physical footprint of N < 2(2t+1)^2 qubits on a square lattice with nearest-neighbor connectivity. The outer-code stabilizer generators XXXX and ZZZZ, each of physical weight 4t, are measured in situ via verified Greenberger-Horne-Zeilinger (GHZ) ancillae distributed through narrow corridors between adjacent patches, without lattice surgery or long-range gates. The outer-code gadgets introduce hyperedge fault mechanisms, but by design each decomposes into graphlike components, so the complete syndrome is decoded by a single minimum-weight-perfect-matching pass. Circuit-level simulations show logical error rates that scale as p^t, consistent with distance-2t protection. Finally, we implement the construction experimentally on a 105-qubit Willow superconducting processor in both the ZZ and XX memory bases. With the correlated-matching decoder, increasing the code distance from d = 4 to d = 6 reduces the block logical error rate by a factor of 1.52. The construction thus provides a near-term testbed for concatenated architectures beyond the standard surface code.

background contribution method result interpretation main claim

What the classifier reports for each sentence. The number is the probability it gave the label.
#sentencerolethe authors' own workstates the main conclusionstrength
s0 We present a fault-tolerant quantum-memory architecture that concatenates four distance-t rotated surface-code patches with the [[4,2,2]] outer code, encoding two logical qubits at code distance d = 2t in a physical footprint of N < 2(2t+1)^2 qubits on a square lattice with nearest-neighbor connectivity. contribution 0.99 0.93 0.30 asserted 1.00
s1 The outer-code stabilizer generators XXXX and ZZZZ, each of physical weight 4t, are measured in situ via verified Greenberger-Horne-Zeilinger (GHZ) ancillae distributed through narrow corridors between adjacent patches, without lattice surgery or long-range gates. method 0.98 0.89 0.08 asserted 1.00
s2 The outer-code gadgets introduce hyperedge fault mechanisms, but by design each decomposes into graphlike components, so the complete syndrome is decoded by a single minimum-weight-perfect-matching pass. method 0.92 0.78 0.08 asserted 1.00
s3 Circuit-level simulations show logical error rates that scale as p^t, consistent with distance-2t protection. result 1.00 0.94 0.14 asserted 0.54
s4 Finally, we implement the construction experimentally on a 105-qubit Willow superconducting processor in both the ZZ and XX memory bases. contribution 0.46 0.95 0.08 asserted 1.00
s5 With the correlated-matching decoder, increasing the code distance from d = 4 to d = 6 reduces the block logical error rate by a factor of 1.52. result 1.00 0.94 0.15 asserted 1.00
s6 The construction thus provides a near-term testbed for concatenated architectures beyond the standard surface code. interpretation 0.97 0.42 0.59 asserted 0.90

What kind of paper the classifier reports this is: method or tool 0.88 · evidence from observation or experiment 0.82.

What was examined, and what was not

sources read
  • arXiv listing abstract v1
not examined
  • full text
  • figures and tables
  • references and citing sentences
  • relations to other papers
levels run
  • P abstract
not run
  • S sections
  • T body sentences
  • C citations
  • R cross-paper relations

Every quoted sentence on this record is the authors'. Every label is from Pith's closed vocabulary, with the probability shown beside it. Every number in the measurements table is the authors', checked by code. Record as JSON

Figures
Figure 1. FIG. 1. Stabilizer structure for the
Figure 2. FIG. 2. A single GHZ preparation round for patch distance
Figure 3. FIG. 3. A single GHZ verification round for patch distance
Figure 4. FIG. 4. Logical error rate
Figure 5. FIG. 5. Logical error rate
Figure 7. FIG. 7. Layout of the stitched-code experiments on the 105-qubit Willow processor,
Figure 8. FIG. 8. Cumulative distributions of physical error probabili
Figure 9. FIG. 9. Experimental logical error probabilities (using correlated matching for decoding) as a function of the number of surface
Figure 10. FIG. 10. Single-point Markov-chain estimates of the per-cycle logical error probabilities
Figure 11. FIG. 11. Same comparison as Fig
Figure 13. FIG. 13. Left: Grouped detection-event fractions for the
Figure 14. FIG. 14. Measured detector statistics vs. the simulated values. Left: Single-detector fire probabilities from Fig.
Figure 15. FIG. 15. Pearson correlation matrices of all detectors for the measured data (left) and the simulated values (right). Detectors
Figure 16. FIG. 16. Left: stitched stability circuit for

Showing 14 of the paper's 16 figures. See all figures in the PDF ↗ Figures reproduced from arXiv:2610.21357 by the authors.

References

Discussion

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