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arxiv: 2605.16010 · v1 · pith:WED2FQ7Pnew · submitted 2026-05-15 · 🪐 quant-ph

Demonstration of a Multiplexing Trapped Ion Quantum Processing Unit

F. Anmasser , M. Abu Zahra , K. Sch\"uppert , M. Pototschnig , J. Wahl , M. Dietl , M. Pfeifer , Y. Colombe
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J. Repp M. Brandl P. Schindler C. R\"ossler
This is my paper

Pith reviewed 2026-05-20 19:20 UTC · model grok-4.3

classification 🪐 quant-ph
keywords trapped ionsquantum computingmultiplexingsample-and-holdsurface ion trapmotional heatingquantum processing unitcontrol electronics
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The pith

Trapped ion quantum processor uses multiplexing to cut control lines while keeping heating low.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper demonstrates a surface ion trap controlled through a time-multiplexed sample-and-hold circuit that charges electrodes from few input lines and then isolates them during operations. The authors measure motional heating rates below one phonon per second in both open and closed switch configurations. They further show that re-sampling every 50 ms or less limits voltage decay so that its contribution to gate error stays below 10 to the minus four. These performance figures indicate the multiplexing approach remains compatible with the high-fidelity gates required for larger quantum processors.

Core claim

The central claim is that a multiplexing scheme based on sample-and-hold allows a trapped-ion quantum processing unit to perform operations with motional heating rates below one phonon per second and expected gate errors from charge decay below 10^{-4} when sampling intervals are under 50 ms.

What carries the argument

The sample-and-hold technique that initially charges trap electrodes to the required voltages from a reduced set of input signals and then disconnects them for the duration of qubit operations.

Load-bearing premise

The electrode voltages remain stable enough during the hold phase that any drift or noise adds no more than 10^{-4} to the gate error.

What would settle it

A measurement showing motional heating rates above one phonon per second or gate errors exceeding the 10^{-4} threshold when the switches remain open for intervals near 50 ms would indicate the multiplexing scheme is not compatible with high-fidelity operations.

Figures

Figures reproduced from arXiv: 2605.16010 by C. R\"ossler, F. Anmasser, J. Repp, J. Wahl, K. Sch\"uppert, M. Abu Zahra, M. Brandl, M. Dietl, M. Pfeifer, M. Pototschnig, P. Schindler, Y. Colombe.

Figure 1
Figure 1. Figure 1: FIG. 1: Illustration of the architectural complexities of trapped-ion quantum computing systems. a) DACs are situated outside [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2: a) High level block diagram of the multiplexer. Inputs of the multiplexer are the DACs, digital control and power [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3: Trap design. a) Stitched microscope image of the sur [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4: Quantum processing units featuring a surface ion trap at their centers and a multiplexer located in the south of [PITH_FULL_IMAGE:figures/full_fig_p008_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5: Experimental setup and socket. a) Sketch of an optical table supporting a vacuum chamber, an EMCCD camera, a [PITH_FULL_IMAGE:figures/full_fig_p009_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6: Temperature dependence of the thin film resistor. [PITH_FULL_IMAGE:figures/full_fig_p010_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7: Voltage drop on electrodes 2 (blue) or 3 (green) vs [PITH_FULL_IMAGE:figures/full_fig_p011_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8: Estimated electrode voltages as a function of [PITH_FULL_IMAGE:figures/full_fig_p012_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9: Axial mode frequency as a function of elapsed time [PITH_FULL_IMAGE:figures/full_fig_p012_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10: Mean phonon numbers for different delays and [PITH_FULL_IMAGE:figures/full_fig_p013_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: FIG. 11: Heating rates as a function of axial frequency and a [PITH_FULL_IMAGE:figures/full_fig_p013_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: FIG. 12: Heating rates as a function of metal temperature and [PITH_FULL_IMAGE:figures/full_fig_p013_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: FIG. 13: Stacked-chip QPU consisting of a multiplexer ASIC and the surface trap glued onto a silicon interposer. The [PITH_FULL_IMAGE:figures/full_fig_p015_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: FIG. 14: a) Colored microscope picture of the second traps electrode design. Shown is a complete unit cell of the design. [PITH_FULL_IMAGE:figures/full_fig_p016_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: FIG. 15: Input-output characteristic for voltage signals going [PITH_FULL_IMAGE:figures/full_fig_p016_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: FIG. 16: All measured heating rates for different metal temperatures and axial secular frequencies. [PITH_FULL_IMAGE:figures/full_fig_p023_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: FIG. 17: Heating rates at different axial frequencies at [PITH_FULL_IMAGE:figures/full_fig_p023_17.png] view at source ↗
Figure 19
Figure 19. Figure 19: FIG. 19: Heating rates at different axial frequencies at [PITH_FULL_IMAGE:figures/full_fig_p024_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: FIG. 20: Ion shuttling simulations for trap type 1 ( [PITH_FULL_IMAGE:figures/full_fig_p025_20.png] view at source ↗
Figure 21
Figure 21. Figure 21: FIG. 21: Microscope picture of the surface ion trap type 2 used for the stacked QPU, with chip dimensions of [PITH_FULL_IMAGE:figures/full_fig_p026_21.png] view at source ↗
read the original abstract

A fault-tolerant quantum computer is expected to require thousands of qubits. Trapped ion architectures provide a modular approach where the quantum register is divided into multiple subregisters connected by physically moving the corresponding ions. Transporting ions at scale comes with several challenges such as the need to connect thousands of control lines to an ion trap chip. Multiplexing the required control voltages from few input signals to multiple electrodes offers a solution to this wiring challenge. Here we demonstrate a quantum processing unit that combines a surface ion trap with a time multiplexer via a sample-and-hold technique that initially charges electrodes to fixed voltages and disconnects them during qubit operations. We characterize the unit's performance by measuring motional heating rates below one phonon per second in both open and closed switch configurations. We further characterize the sample and hold process and find that sampling intervals below 50 ms are sufficient to keep expected gate errors from decaying charges during the hold phase below $10^{-4}$. Our results indicate that the multiplexing scheme is compatible with high-fidelity operations.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 2 minor

Summary. The manuscript demonstrates a multiplexing trapped ion quantum processing unit that integrates a surface ion trap with a time-multiplexer using a sample-and-hold technique. Electrodes are charged to fixed voltages and then disconnected during qubit operations to address wiring scalability. The authors report direct measurements of motional heating rates below one phonon per second in both open and closed switch configurations, and characterize sampling intervals below 50 ms as sufficient to keep modeled gate errors from decaying charges below 10^{-4}, concluding that the scheme is compatible with high-fidelity operations.

Significance. If the error estimates hold, this addresses a critical wiring bottleneck for scaling trapped-ion systems to thousands of qubits in modular architectures. The direct heating-rate measurements in both switch states provide concrete experimental support for compatibility, independent of fitted models, and the work offers a practical path toward reduced control-line counts without immediate fidelity loss.

major comments (1)
  1. [Abstract and sample-and-hold characterization] Abstract and sample-and-hold characterization section: The central claim that multiplexing contributes less than 10^{-4} gate error rests on an estimate of voltage drift from charge decay during the hold phase. However, this estimate is derived from a model without reported direct in-situ measurements of electrode potential, noise spectra, or drift while the ion is trapped and laser-addressed. Direct verification would be needed to rule out contributions from switch leakage, EMI, or unmodeled effects that could exceed the modeled budget.
minor comments (2)
  1. [Abstract] The abstract states heating rates below one phonon per second but does not include statistical uncertainties, number of measurements, or full error budgets for these values.
  2. [Sample-and-hold characterization] Clarify the precise functional form and assumptions used to convert sampling interval to expected gate error from decaying charges (e.g., any dependence on electrode capacitance or leakage current).

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their constructive review and for recognizing the potential significance of our multiplexing approach for scaling trapped-ion systems. We address the major comment point by point below.

read point-by-point responses

  1. Referee: Abstract and sample-and-hold characterization section: The central claim that multiplexing contributes less than 10^{-4} gate error rests on an estimate of voltage drift from charge decay during the hold phase. However, this estimate is derived from a model without reported direct in-situ measurements of electrode potential, noise spectra, or drift while the ion is trapped and laser-addressed. Direct verification would be needed to rule out contributions from switch leakage, EMI, or unmodeled effects that could exceed the modeled budget.

    Authors: We appreciate the referee drawing attention to the distinction between modeled voltage drift and direct experimental verification. The gate-error estimate is obtained from the product of the measured sampling interval, the electrode capacitance, and the leakage current of the sample-and-hold circuitry (determined from component specifications and bench measurements). While we do not report direct in-situ electrode-potential measurements during ion trapping and laser addressing, such measurements are technically challenging without introducing additional conductors or sensors that could themselves perturb the electric-field environment. Instead, we rely on the direct motional-heating-rate measurements performed with the ion present and the lasers active. These rates remain below 1 phonon/s in both the open-switch and closed-switch configurations, providing an experimental upper bound on any excess electric-field noise or slow drifts attributable to the multiplexer. Because motional heating is the dominant error channel linked to electrode-voltage fluctuations in our system, the absence of measurable excess heating supports the claim that unmodeled contributions from leakage, EMI, or other effects remain within the budgeted error. In the revised manuscript we will add a paragraph in the sample-and-hold characterization section that explicitly connects the heating-rate data to the modeled drift budget and states the assumptions underlying the leakage-current estimate. revision: partial

Circularity Check

0 steps flagged

No significant circularity: experimental characterization stands independently

full rationale

The paper reports direct experimental measurements of motional heating rates below one phonon per second in open and closed switch configurations, along with empirical characterization of sampling intervals below 50 ms to bound expected gate errors from charge decay below 10^{-4}. These results derive from in-situ ion trap observations rather than any mathematical derivation, fitted parameter renamed as prediction, or self-citation chain that reduces the central claim to its own inputs. No equations or uniqueness theorems are invoked that loop back by construction; the compatibility conclusion follows from the reported data without self-referential reduction.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The work rests on standard trapped-ion physics assumptions plus the domain assumption that hold-phase voltage stability is sufficient for the target error level.

axioms (1)
  • domain assumption Sample-and-hold voltage stability during disconnection is adequate to keep gate errors below 10^{-4}
    Invoked when estimating error from decaying charges for sampling intervals below 50 ms.

pith-pipeline@v0.9.0 · 5759 in / 1156 out tokens · 33876 ms · 2026-05-20T19:20:02.979122+00:00 · methodology

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