Paper Citation Record · LEDGER

Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 11 inbound Pith citation observations for arXiv:2408.11053.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2408.11053 v2

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 11 of 11 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00

measured 11 of 11 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-07T10:45:07.093846Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-03T19:08:49.846394Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 29da22fa-84f2-4fec-852f-6c326b303e99 · inbound

hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation cites this paper.

hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-07T10:45:07.093846Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e3599c72-cd69-4338-945a-42a057a0a49a · inbound

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs cites this paper.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 28

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:53.956140Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 09dc13c3-c7ea-4364-bdf8-502aeafa3a8e · inbound

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning cites this paper.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:24.367469Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9fbc4818-8d3f-448f-b375-8ac0544a7e9d · inbound

LEGO: An LLM Skill-Based Front-End Design Generation Platform cites this paper.

LEGO: An LLM Skill-Based Front-End Design Generation Platform Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 2

Resolution: verified exact; arxiv_id, observed 2026-05-11T20:41:10.275700Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ae7451e5-aae2-4b27-ba5b-60b3a76d8db8 · inbound

LEGO: An LLM Skill-Based Front-End Design Generation Platform cites this paper.

LEGO: An LLM Skill-Based Front-End Design Generation Platform Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 2

Resolution: verified exact; arxiv_id, observed 2026-05-21T09:19:56.727585Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 22bbada9-d4e1-4e6d-8938-0f61a7510787 · inbound

ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation cites this paper.

ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 19

Resolution: verified exact; arxiv_id, observed 2026-06-30T22:05:05.880846Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 77394ed8-6091-4f9b-8004-17167dafae0d · inbound

RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision cites this paper.

RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 14

Resolution: verified exact; arxiv_id, observed 2026-05-19T14:42:37.327335Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation c51933ed-f1d4-4647-9eb7-817f9c215108 · inbound

Forgetting in Language Models: Capacity, Optimization, and Self-Generated Replay cites this paper.

Forgetting in Language Models: Capacity, Optimization, and Self-Generated Replay Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 32

Resolution: verified exact; arxiv_id, observed 2026-06-29T23:24:01.984466Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 13018004-98c7-48c8-9a35-5ea85ec5a26c · inbound

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation cites this paper.

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 27

Resolution: verified exact; arxiv_id, observed 2026-06-29T18:53:51.245169Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 008be894-4bf0-4a57-8aeb-47b0309656c1 · inbound

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models cites this paper.

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 28

Resolution: verified exact; arxiv_id, observed 2026-07-03T00:47:30.498364Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 2d844b85-5e81-40c6-86f2-fa2884421131 · inbound

PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design cites this paper.

PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 23

Resolution: verified exact; arxiv_id, observed 2026-07-03T19:08:49.847891Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.