Paper Citation Record · LEDGER

BetterV: Controlled Verilog Generation with Discriminative Guidance

As of 7 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 19 inbound Pith citation observations for arXiv:2402.03375.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2402.03375 v3

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 19 of 19 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00

measured 19 of 19 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-07T10:34:04.402809Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-03T04:37:37.432531Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 87bd107b-e229-425b-9246-f51ff3b768b4 · inbound

QiMeng: Fully Automated Hardware and Software Design for Processor Chip cites this paper.

QiMeng: Fully Automated Hardware and Software Design for Processor Chip BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 42

Resolution: unresolved; no resolver link, observed 2026-08-07T10:34:04.402809Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 46619f58-befa-47df-8bf0-42e566178bfb · inbound

ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation cites this paper.

ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 28

Resolution: unresolved; no resolver link, observed 2026-08-07T10:19:00.756053Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 050b484b-e20b-4524-8ef6-868334f1cc7c · inbound

DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs cites this paper.

DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-06T20:40:18.323151Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation eae65f8f-a36b-4171-b829-ed307dbfac44 · inbound

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation cites this paper.

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 31

Resolution: unresolved; no resolver link, observed 2026-08-06T18:54:05.126668Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation cfdde7b4-8bdf-4618-8ba2-d2927251a295 · inbound

VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs cites this paper.

VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-06T15:51:34.440581Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8b535f76-efe3-42bc-9363-9b88b2a1966e · inbound

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs cites this paper.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:52.329639Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 87d074cb-e1a7-4974-9522-bde272d5f7aa · inbound

Principle-Guided Verilog Optimization: IP-Safe Knowledge Transfer via Local-Cloud Collaboration cites this paper.

Principle-Guided Verilog Optimization: IP-Safe Knowledge Transfer via Local-Cloud Collaboration BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 2024

Resolution: unresolved; no resolver link, observed 2026-08-06T04:42:23.009878Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c91e2155-1fd0-4cf1-8d63-646b441bab22 · inbound

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code cites this paper.

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-04T20:43:14.334778Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 7a287d9c-b024-4552-a041-e6dfe96ba69c · inbound

Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement cites this paper.

Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 28

Resolution: verified exact; arxiv_id, observed 2026-05-10T10:49:56.182189Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 075beb1c-8a85-4417-b6b7-b9a06dde7996 · inbound

COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation cites this paper.

COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 22

Resolution: verified exact; arxiv_id, observed 2026-05-10T10:34:28.892384Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 1bc068b8-e86a-454c-a87f-49ee7c942212 · inbound

VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation cites this paper.

VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 17

Resolution: verified exact; arxiv_id, observed 2026-05-11T12:11:07.003374Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 682c4596-b54e-472e-b2ea-bdadadfcd316 · inbound

AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning cites this paper.

AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 18

Resolution: metadata mismatch; arxiv_id, observed 2026-05-10T12:10:23.054069Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 62a79e9b-83b8-415a-af8b-0dc47acf4dee · inbound

RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision cites this paper.

RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 13

Resolution: verified exact; arxiv_id, observed 2026-05-19T14:42:37.297711Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 6cf08885-a739-4266-b85c-87bbc6c85e8d · inbound

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation cites this paper.

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 3

Resolution: verified exact; arxiv_id, observed 2026-06-29T18:53:51.259427Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 950543c9-8013-4668-aa32-cb9707fd75e9 · inbound

Alpha-RTL: Test-Time Training for RTL Hardware Optimization cites this paper.

Alpha-RTL: Test-Time Training for RTL Hardware Optimization BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 30

Resolution: metadata mismatch; arxiv_id, observed 2026-07-02T07:06:44.134199Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ea71b236-fd20-484f-a3ee-18c03a440349 · inbound

ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards cites this paper.

ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 11

Resolution: verified exact; arxiv_id, observed 2026-07-02T20:27:22.716254Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation d35c0577-c627-468a-b9df-023e9caafe9e · inbound

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models cites this paper.

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 27

Resolution: verified exact; arxiv_id, observed 2026-07-03T00:47:30.515700Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e2d4e862-ab4d-43d8-b83d-d2c4ad0414c2 · inbound

OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design cites this paper.

OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 31

Resolution: verified exact; arxiv_id, observed 2026-07-03T04:37:37.434099Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 6d8e2632-eb25-4f50-ae7a-eabd3b59c0e8 · inbound

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation cites this paper.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.766837Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.