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arxiv: 2606.30592 · v1 · pith:LJJHCQRVnew · submitted 2026-06-29 · 🪐 quant-ph

Untangling QLDPC Codes with Biased Noise Ancilla

Runjiang Bi , Kathleen Chang , Shruti Puri This is my paper

Pith reviewed 2026-06-30 05:53 UTC · model grok-4.3

classification 🪐 quant-ph
keywords QLDPC codesbiased noisesyndrome extractionhook errorsfault distancelogical error rateTanner graph
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The pith

Biased noise on ancilla qubits can raise the effective fault distance of QLDPC syndrome extraction and lower logical error rates by nearly an order of magnitude.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that for certain QLDPC codes, using ancillas that only suffer phase-flip errors instead of full depolarizing noise improves the performance of standard syndrome extraction circuits. This happens because it reduces hook errors and short loops in the Tanner graph. At a circuit noise level of 2 times 10 to the minus 3, with bit-flip errors on ancillas 50 times less likely than phase-flips, the logical error rate improves by almost ten times. This approach applies to bicycle bivariate codes and cyclic hypergraph product codes without needing new circuit designs. A sympathetic reader would care because it offers a hardware-aware way to make high-rate QLDPC codes more practical for error correction.

Core claim

When ancillas are subject to phase-flip errors only, the effective fault-distance of the conventional syndrome extraction circuit is significantly higher and the number of short loops is significantly lower compared to when they are also subject to bit-flip errors, resulting in almost an order of magnitude improvement in the logical error rate at circuit noise of 2×10^{-3} when bit-flip errors in the ancilla are 50 times less likely than phase-flip errors.

What carries the argument

Biased noise ancillas limited to phase-flip errors in the syndrome extraction circuit for QLDPC codes.

If this is right

  • The effective fault-distance increases for bicycle bivariate codes and cyclic hypergraph product codes.
  • The number of short loops in the Tanner graph decreases.
  • Logical error rates improve by nearly an order of magnitude under the specified noise conditions.
  • This provides a practical advantage without changing the circuit structure.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Hardware implementations that can bias ancilla noise toward phase flips while keeping data qubits depolarizing could enable better QLDPC performance.
  • Similar bias techniques might apply to other quantum codes beyond the examples studied.
  • Decoders could be optimized further if short loops are reduced this way.

Load-bearing premise

Ancilla qubits can be realized with phase-flip errors only, specifically with bit-flip rates 50 times lower than phase-flip rates, while the rest of the circuit has standard depolarizing noise.

What would settle it

A simulation or experiment showing that the logical error rate does not improve by nearly an order of magnitude when ancilla bit-flip errors are suppressed by a factor of 50 at 2e-3 circuit noise would falsify the claim.

Figures

Figures reproduced from arXiv: 2606.30592 by Kathleen Chang, Runjiang Bi, Shruti Puri.

Figure 1
Figure 1. Figure 1: FIG. 1. Syndrome extraction circuits. Data qubits are in black, [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. Logical error rates per round versus physical noise [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Comparing finite-bias ( [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. The [[336 [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
read the original abstract

Remarkable technical progress has made high-rate, high-distance, quantum low-density parity-check codes (QLDPC) promising candidates for scalable quantum computing. However, it is hard to design low-depth syndrome extraction circuits that do not spread errors from ancilla qubits to multiple data qubits, also known as hook errors, for general QLDPC codes. Additionally, widely used decoders for these codes based on belief propagation are impaired due to short loops in the Tanner graph. Here, we investigate a hardware-aware approach to avoid these hooks and loops using biased noise ancillas. Using examples of bicycle bivariate codes and a cyclic hypergraph product code, which have been widely considered for practical application, we show that the effective fault-distance of the conventional syndrome extraction circuit can be significantly higher and the number of short loops can be significantly lower when the ancillas are subject to phase-flip errors only, compared to when they are also subject to bit-flip errors. This can result in almost an order of magnitude improvement in the logical error rate at circuit noise of $2\times 10^{-3}$ and when bit-flip errors in the ancilla are 50 times less likely than phase-flip errors. Our work demonstrates a significant and practical quantum error correction advantage with biased noise qubits in which full-bias cannot be maintained.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript investigates a hardware-aware approach to mitigating hook errors and short Tanner-graph loops in syndrome extraction circuits for QLDPC codes by restricting ancilla noise to phase flips only (with bit-flip rate 50× lower than phase-flip rate). Using bicycle bivariate codes and a cyclic hypergraph product code, it reports that this bias raises the effective fault distance of conventional circuits, reduces short loops, and yields nearly an order-of-magnitude improvement in logical error rate at circuit-level noise p=2×10^{-3} under depolarizing noise on data qubits.

Significance. If the ancilla-only bias model holds, the work supplies a practical route to better performance for existing high-rate, high-distance QLDPC constructions without new code designs or decoders. The concrete numerical gains at realistic noise levels and the focus on codes already considered for implementation are strengths.

major comments (2)
  1. [Abstract and noise-model description] The central performance claims (higher effective fault distance, fewer short loops, ~10× logical-error-rate improvement) are obtained exclusively under the circuit-level noise model in which ancillas experience phase-flip errors only while data qubits see full depolarizing noise. No section provides an independent hardware argument, calibration data, or analysis showing that a 50× bit-flip suppression can be maintained on ancillas alone without side effects from two-qubit gates or readout that would couple the bias to data qubits.
  2. [Results on bicycle and hypergraph-product codes] The reported distance and loop-count advantages are presented as numerical observations from simulation; the manuscript does not derive or bound how the bias alters the effective distance or loop structure analytically (e.g., via modified error propagation in the syndrome-extraction circuit).
minor comments (1)
  1. Notation for the biased noise model (e.g., the precise definition of the 50× ratio and how it is applied to each gate type) should be stated explicitly in the methods section rather than only in the abstract.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for their careful reading of the manuscript and for recognizing the practical relevance of biased-noise ancillas for existing QLDPC constructions. We address each major comment below.

read point-by-point responses

  1. Referee: [Abstract and noise-model description] The central performance claims (higher effective fault distance, fewer short loops, ~10× logical-error-rate improvement) are obtained exclusively under the circuit-level noise model in which ancillas experience phase-flip errors only while data qubits see full depolarizing noise. No section provides an independent hardware argument, calibration data, or analysis showing that a 50× bit-flip suppression can be maintained on ancillas alone without side effects from two-qubit gates or readout that would couple the bias to data qubits.

    Authors: We acknowledge that the reported gains rely on the assumed biased-noise model for ancillas (phase flips only, with bit-flip rate 50× lower). The manuscript frames this as a hardware-aware model motivated by prior work on biased-noise qubits, but does not supply new hardware calibration data or analysis of potential side effects from gates or readout that could couple bias to data qubits. This limitation is inherent to the scope of the present numerical study. We will revise the abstract and introduction to state more explicitly that the 50× suppression is an input assumption of the noise model rather than a demonstrated hardware property. revision: partial

  2. Referee: [Results on bicycle and hypergraph-product codes] The reported distance and loop-count advantages are presented as numerical observations from simulation; the manuscript does not derive or bound how the bias alters the effective distance or loop structure analytically (e.g., via modified error propagation in the syndrome-extraction circuit).

    Authors: The improvements in effective fault distance and the reduction in short Tanner-graph loops are obtained from direct simulation of the syndrome-extraction circuits under the biased ancilla model. We supply circuit-level explanations of the underlying mechanisms (elimination of bit-flip-induced hooks that would otherwise produce uncorrectable weight-2 errors), but we do not provide analytical bounds on the modified distance or loop spectrum. Deriving such bounds for general QLDPC codes under circuit noise remains an open theoretical challenge. We will expand the discussion section with additional detail on the observed error-propagation patterns that underlie the numerical results. revision: partial

standing simulated objections not resolved
  • Independent hardware argument, calibration data, or analysis demonstrating that a 50× bit-flip suppression can be maintained on ancillas without side effects from two-qubit gates or readout.

Circularity Check

0 steps flagged

No circularity; central claims are direct numerical observations from simulations under an explicit noise model

full rationale

The paper reports simulation results on effective fault distance, Tanner-graph loop counts, and logical error rates for specific QLDPC codes under two noise models (depolarizing vs. ancilla phase-flip only). These quantities are computed directly from circuit-level Monte Carlo or similar methods; no equations, fitted parameters, or self-citations are invoked to derive the reported improvements. The modeling choice of 50× bit-flip suppression on ancillas is stated as an input assumption rather than derived, and the performance numbers are presented as empirical outcomes rather than self-referential predictions. No load-bearing self-citation chain or renaming of known results appears in the derivation.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only; no free parameters, axioms, or invented entities can be extracted or audited.

pith-pipeline@v0.9.1-grok · 5762 in / 1119 out tokens · 27449 ms · 2026-06-30T05:53:08.033405+00:00 · methodology

discussion (0)

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Reference graph

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