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Every paper Pith has read. Search by title, abstract, or pith.
493 papers in cs.AR · page 2
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Analog recurrence works at sub-microwatt power via bistable units
Hardware-Software Co-Design of Scalable, Energy-Efficient Analog Recurrent Computations
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Calibration feedback control cuts optimization gaps in local and tight-loop regimes
Runtime Calibration as State-Trajectory Feedback Control in Quantum-Classical Workflows
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Cumulative updates fix gradient flow in low-power RNNs
Improving the Performance and Learning Stability of Parallelizable RNNs Designed for Ultra-Low Power Applications
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Dynamic scheduler lifts MoE inference 1.3-1.6x on PIM hardware
Sieve: Dynamic Expert-Aware PIM Acceleration for Evolving Mixture-of-Experts Models
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Triton gains direct warp-group control for modern GPU hardware
TLX: Hardware-Native, Evolvable MIMW GPU Compiler for Large-scale Production Environments
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TLX adds MIMW warp-group control to Triton for modern GPUs
TLX: Hardware-Native, Evolvable MIMW GPU Compiler for Large-scale Production Environments
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LLMs generate hardware code but introduce security risks
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
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LLMs automate chip design but create security risks
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
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LLMs Generate RTL Code but Create New Hardware Risks
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
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Hybrid chip runs GNN at 2.94M events/sec for physics triggers
Reconfigurable Computing Challenge: Real-Time Graph Neural Networks for Online Event Selection in Big Science
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Error profiles detect stolen approximate circuit IP despite mimicry
ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits
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Piezoelectric sensors turn desk vibrations into six-gesture commands
Towards an End-To-End System for Real-Time Gesture Recognition from Surface Vibrations
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Hardware assertion sets reduced by 76 percent
Arcane: An Assertion Reduction Framework through Semantic Clustering and MCTS-Guided Rule Exploring
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LLM agents size RF amplifiers via resource allocation
RFAmpDesigner: A Self-Evolving Multi-Agent LLM Framework for Automated Radio Frequency Amplifier Design
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KV-cache movement regularization cuts static-graph LLM latency spikes
KV-RM: Regularizing KV-Cache Movement for Static-Graph LLM Serving
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Wafer integration of three 2D devices decides next computing decade
Emerging 2D Materials for Beyond von Neumann Computing: A Perspective
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LLM accuracy depends only on evicted tokens
Not All Thoughts Need HBM: Semantics-Aware Memory Hierarchy for LLM Reasoning
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ReRAM-on-logic chip reaches 14-136 tokens per second on LLMs
31.1 A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding
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Memoized heuristics scale ion-trap qubit mapping
Scaling Qubit Mapping and Routing With Position Graph Abstraction and Memoization
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Complex GAN metric separates gate-failure effects in circuits
Fault tolerance estimation in digital circuits with visualised generative networks
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MPS decoding latency spikes up to 21x in narrow ranges
Non-Monotonic Latency in Apple MPS Decoding: KV Cache Interactions and Execution Regimes
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Apple MPS shows 21x latency spikes in narrow decoding ranges
Non-Monotonic Latency in Apple MPS Decoding: KV Cache Interactions and Execution Regimes
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New cache bypass method meets deadlines while boosting heterogeneous system speed
HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators
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HyDRA balances accelerator deadlines with cache reuse via clustering
HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators
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Low-complexity denoiser matches heavy mmWave MIMO methods
Low-Complexity Beamspace Channel Denoiser for mmWave Massive MIMO with Low-Resolution ADCs
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Reconfigurable multiplier cuts power 44-68% in RISC-V core
A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
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DDR5 single sub-channel matches cache lines but loses 40-60% bandwidth
Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation
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Edge processor hits 109 TFLOPS/W on DeepSeek
DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing
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Coprime test vectors localize faulty rows in systolic arrays after one pass
FLARE: One-Shot PE-Level Fault Localization in Systolic Arrays via Algebraic Test Vectors
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Static checker decides barrier sufficiency for accelerator races
AccelSync: Verifying Synchronization Coverage in Accelerator Pipeline Programs
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Model runs 1024-core chip sims 115x faster at under 7% error
Accelerating Precise End-to-End Simulation: Latency-Sensitive Many-core System Modeling
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Plasma simulations need three post-Moore tech tiers
Post-Moore Technologies for Plasma Simulation: A Community Roadmap
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GNNs for EDA succeed when matched to each task's native algebra
Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation
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Bit-hardening methods surpass ECC for reliable DNNs with no memory cost
Effective and Memory-Efficient Alternatives to ECC for Reliable Large-Scale DNNs
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TREA accelerator reduces edge detection latency up to 9x
TREA: Low-precision Time-Multiplexed, Resource-Efficient Edge Accelerator for Object Detection and Classification
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Reconfigurable FPU gives up to 8x throughput for low-precision dot products
TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines
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Open schema and datasets released for ML benchmarks in chip design
EDA-Schema-V2: A Multimodal Schema, Open Datasets, and Benchmarks for Machine Learning in Digital Physical Design
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Agents reach just 20% success on multi-PPA in new benchmark
Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing
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Agents solve only 37% of practical chip design rule problems
Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing
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CORDIC iteration depth trims 33 percent of inference cycles
CARMEN: CORDIC-Accelerated Resource-Efficient Multi-Precision Inference Engine for Deep Learning
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Posit engine cuts ADAS power by 72 percent with near full accuracy
EULER-ADAS: Energy-Efficient & SIMD-Unified Logarithmic-Posit Engine for Precision-Reconfigurable Approximate ADAS Acceleration
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FPGA YOLOv3-Tiny system detects in 0.211 seconds
Development of embedded target detection system based on FPGA and YOLOv3-Tiny
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Self-supervised pretraining yields tiny wildfire spotters for satellites
On-Orbit Real-Time Wildfire Detection Under On-Board Constraints
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Pipeline speeds power-of-two DNNs on edge FPGAs by up to 3.6x
PoTAcc: A Pipeline for End-to-End Acceleration of Power-of-Two Quantized DNNs
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FPGA MAC unifies mixed-precision ops for 1.2x LLM speedup
XtraMAC: An Efficient MAC Architecture for Mixed-Precision LLM Inference on FPGA
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Photonic solver beats digital annealers on dense spin-glasses
A virtually connected probabilistic computer as a solver for higher-order, densely connected, or reconfigurable combinatorial optimisation problems
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LLMs automate FPGA accelerator design space exploration
LLM-Driven Design Space Exploration of FPGA-based Accelerators
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Hardware hub lets MoE send data before knowing GPU addresses
MoE-Hub: Taming Software Complexity for Seamless MoE Overlap with Hardware-Accelerated Communication on Multi-GPU Systems
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Heterogeneous HBM-PIM stack lifts LLM throughput 1.62x
TokenStack: A Heterogeneous HBM-PIM Architecture and Runtime for Efficient LLM Inference
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New in-switch method delivers 1.38x faster LLM tensor parallel training
Towards Compute-Aware In-Switch Computing for LLMs Tensor-Parallelism on Multi-GPU Systems