ChipNeMo: Domain-Adapted LLMs for Chip Design | Paper Citation Record

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Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI cites this paper.

Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 10

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LLMPirate: LLMs for Black-box Hardware IP Piracy cites this paper.

LLMPirate: LLMs for Black-box Hardware IP Piracy ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 43

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UVLLM: An Automated Universal RTL Verification Framework using LLMs cites this paper.

UVLLM: An Automated Universal RTL Verification Framework using LLMs ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 14

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RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation cites this paper.

RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 12

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EDA-Aware RTL Generation with Large Language Models cites this paper.

EDA-Aware RTL Generation with Large Language Models ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 1

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On the effective transfer of knowledge from English to Hindi Wikipedia cites this paper.

On the effective transfer of knowledge from English to Hindi Wikipedia ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 19

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MAGE: A Multi-Agent Engine for Automated RTL Code Generation cites this paper.

MAGE: A Multi-Agent Engine for Automated RTL Code Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 16

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SuperCode: Sustainability PER AI-driven CO-DEsign cites this paper.

SuperCode: Sustainability PER AI-driven CO-DEsign ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 34

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AiEDA: Agentic AI Design Framework for Digital ASIC System Design cites this paper.

AiEDA: Agentic AI Design Framework for Digital ASIC System Design ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 7

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CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generation cites this paper.

CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 14

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TelcoLM: collecting data, adapting, and benchmarking language models for the telecommunication domain cites this paper.

TelcoLM: collecting data, adapting, and benchmarking language models for the telecommunication domain ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 25

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Observation 34b0e947-1c03-494f-84a2-15495c6af29d · inbound

ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation cites this paper.

ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 14

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Observation b4a34495-09aa-498c-b691-042258fa2f7c · inbound

AGON: Automated Design Framework for Customizing Processors from ISA Documents cites this paper.

AGON: Automated Design Framework for Customizing Processors from ISA Documents ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 50

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Observation 734068f0-e1d5-4a51-bc6c-b44eb7b2e300 · inbound

HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers cites this paper.

HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 30

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A Survey of Research in Large Language Models for Electronic Design Automation cites this paper.

A Survey of Research in Large Language Models for Electronic Design Automation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 33

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Observation 048ec5db-0bc3-4810-9337-7d7c54c608c7 · inbound

Paradigm-Based Automatic HDL Code Generation Using LLMs cites this paper.

Paradigm-Based Automatic HDL Code Generation Using LLMs ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 13

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Observation c68d8d40-6e50-4334-8b9f-157d47d58147 · inbound

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency cites this paper.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:06.912772Z

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Observation 5a7f2889-c2de-49ff-a6dd-4d55e3186ec1 · inbound

VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation cites this paper.

VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 1

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Observation 18d48241-51c3-4295-bb3f-7e1cd1abe029 · inbound

SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Design cites this paper.

SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Design ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 8

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Observation 4aa35965-42a3-417f-992d-d0c4d8bc8a26 · inbound

Deep Representation Learning for Electronic Design Automation cites this paper.

Deep Representation Learning for Electronic Design Automation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 52

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Observation 329d3e58-f3ae-41d8-858c-75595eaf0e6d · inbound

Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors cites this paper.

Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 3

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Observation db7dd468-c459-4b4b-92d5-c2bef169f1cd · inbound

VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation cites this paper.

VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 7

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Observation bf4d0259-9c38-4104-9530-139bf18e52e7 · inbound

RTL++: Graph-enhanced LLM for RTL Code Generation cites this paper.

RTL++: Graph-enhanced LLM for RTL Code Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 26

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Observation c30b3468-dfe9-459f-828e-11caee1e7a4f · inbound

JARVIS: A Multi-Agent Code Assistant for High-Quality EDA Script Generation cites this paper.

JARVIS: A Multi-Agent Code Assistant for High-Quality EDA Script Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 14

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Observation 1efcae57-5a48-4b53-8288-8174b3c25b30 · inbound

Large Processor Chip Model cites this paper.

Large Processor Chip Model ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 10

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Observation 8709c41c-5ea0-4614-841a-2f1e946dd382 · inbound

QiMeng: Fully Automated Hardware and Software Design for Processor Chip cites this paper.

QiMeng: Fully Automated Hardware and Software Design for Processor Chip ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 40

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Improving LLM-Powered EDA Assistants with RAFT cites this paper.

Improving LLM-Powered EDA Assistants with RAFT ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 3

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Observation 5c463dec-6ff9-4442-ac68-2deabe2ddb34 · inbound

ORFS-agent: Tool-Using Agents for Chip Design Optimization cites this paper.

ORFS-agent: Tool-Using Agents for Chip Design Optimization ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 34

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Observation 7457b8ea-3bfe-48f0-b7e6-974eca57251e · inbound

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems cites this paper.

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 19

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Observation 0f9544b8-b7ea-4cf4-9c72-4914bd5024ba · inbound

Controlling Context: Generative AI at Work in Integrated Circuit Design and Other High-Precision Domains cites this paper.

Controlling Context: Generative AI at Work in Integrated Circuit Design and Other High-Precision Domains ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 88

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Observation 839bcfdf-a8e5-473f-b830-8521ffc9377b · inbound

CoVE: Compressed Vocabulary Expansion Makes Better LLM-based Recommender Systems cites this paper.

CoVE: Compressed Vocabulary Expansion Makes Better LLM-based Recommender Systems ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 58

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Observation c77d895e-bf08-40f0-9a46-664ca1ce78ac · inbound

Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization cites this paper.

Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 9

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VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs cites this paper.

VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-06T15:51:34.443963Z

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Observation e3cfb70a-f518-49b2-a5a2-0e6b4e8297e6 · inbound

AnalogFed: Privacy-Preserving Discovery of Analog Circuits at Scale with Federated Generative AI cites this paper.

AnalogFed: Privacy-Preserving Discovery of Analog Circuits at Scale with Federated Generative AI ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-06T15:46:52.306589Z

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Observation f498e9d2-442d-4d49-b3b7-b86199dfd14f · inbound

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs cites this paper.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 3

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Observation 22a39c2f-567a-43f2-981d-f245ad845bac · inbound

TD-Interpreter: Enhancing the Understanding of Timing Diagrams with Visual-Language Learning cites this paper.

TD-Interpreter: Enhancing the Understanding of Timing Diagrams with Visual-Language Learning ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-06T15:47:16.050716Z

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Observation a419aeb3-04f8-4616-8ac4-741362428b3c · inbound

MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs cites this paper.

MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 1

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Observation 080b4bb0-8274-4c8b-a57b-151e6778a486 · inbound

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization cites this paper.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 12

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Observation 24b2c6a6-704a-4d0d-ac56-820639849178 · inbound

EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code cites this paper.

EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-06T22:33:16.045541Z

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Observation 1c37ef7d-051f-4b90-8f92-b34ed77ba6e7 · inbound

AI Agents for Photonic Integrated Circuit Design Automation cites this paper.

AI Agents for Photonic Integrated Circuit Design Automation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 24

Resolution: unresolved; no resolver link, observed 2026-08-15T17:20:07.041839Z

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Observation 66784273-8fd1-4643-8000-716b39dad172 · inbound

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning cites this paper.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 37

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Observation 0dca62c8-f567-4a86-a3d8-d1f43838059d · inbound

GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification cites this paper.

GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 20

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Observation c732ae9d-b738-4392-908c-b06fd4192373 · inbound

Revolution or Hype? Seeking the Limits of Large Models in Hardware Design cites this paper.

Revolution or Hype? Seeking the Limits of Large Models in Hardware Design ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 22

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Observation 46b5e136-0550-46e8-b01d-d7340d7cce24 · inbound

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design cites this paper.

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 24

Resolution: unresolved; no resolver link, observed 2026-08-04T16:31:32.483801Z

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Observation e46a6dd1-4559-4f4e-b119-e62ad1ebbfeb · inbound

Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization cites this paper.

Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-02T18:17:31.071509Z

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Observation 7d1f6c68-4538-4543-8d0c-6dfb2caa38e7 · inbound

FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification cites this paper.

FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 8

Resolution: metadata mismatch; arxiv_id, observed 2026-05-15T14:35:55.951522Z

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No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation c213a339-dff1-4b2d-8f4e-435b1eb5e232 · inbound

FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification cites this paper.

FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-02T18:43:42.900544Z

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Observation a3feb579-92b8-4431-b723-9a21f1b3ce4e · inbound

Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design cites this paper.

Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 31

Resolution: verified exact; arxiv_id, observed 2026-05-11T00:25:50.584105Z

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Observation 91486680-4756-449c-ae9d-756a8a90e57b · inbound

TensorLift: Automatic Extraction of Tensor-Level ISA Semantics from Accelerator RTL via MLIR Semantic Lifting cites this paper.

TensorLift: Automatic Extraction of Tensor-Level ISA Semantics from Accelerator RTL via MLIR Semantic Lifting ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 30

Resolution: verified exact; arxiv_id, observed 2026-05-11T11:46:20.371356Z

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Observation ac99d122-614f-4154-9580-2e0a47f7d23a · inbound

COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation cites this paper.

COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 15

Resolution: metadata mismatch; arxiv_id, observed 2026-05-10T10:34:28.877695Z

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No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation 04db953c-9080-4d9d-b375-be4e50f173a6 · inbound

Structural Verification for Reliable EDA Code Generation without Tool-in-the-Loop Debugging cites this paper.

Structural Verification for Reliable EDA Code Generation without Tool-in-the-Loop Debugging ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 10

Resolution: metadata mismatch; arxiv_id, observed 2026-05-11T12:21:04.109633Z

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Observation 0e41e962-e2af-46d0-9bec-6e9295ce94c7 · inbound

Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models cites this paper.

Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 57

Resolution: metadata mismatch; arxiv_id, observed 2026-05-09T23:04:17.786077Z

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Observation 9664b8a5-b618-4d18-8489-6c79b9d2759d · inbound

LEGO: An LLM Skill-Based Front-End Design Generation Platform cites this paper.

LEGO: An LLM Skill-Based Front-End Design Generation Platform ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 6

Resolution: metadata mismatch; arxiv_id, observed 2026-05-11T20:41:10.244597Z

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Observation 5a2e03f7-98cf-4f57-9761-2642a53d8e47 · inbound

LEGO: An LLM Skill-Based Front-End Design Generation Platform cites this paper.

LEGO: An LLM Skill-Based Front-End Design Generation Platform ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 6

Resolution: metadata mismatch; arxiv_id, observed 2026-05-21T09:19:56.721693Z

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Observation 1f92ed4d-c71b-4d86-bd3b-a53e8922a7b4 · inbound

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog cites this paper.

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 10

Resolution: metadata mismatch; arxiv_id, observed 2026-05-11T21:31:14.800195Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation e5110ecb-bac9-48e9-8faf-0e3354783c0e · inbound

RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation cites this paper.

RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 7

Resolution: metadata mismatch; arxiv_id, observed 2026-05-11T22:11:14.596825Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation 33d57c97-faaf-42bf-ae2b-ccb01156590e · inbound

ChipLingo: A Systematic Training Framework for Large Language Models in EDA cites this paper.

ChipLingo: A Systematic Training Framework for Large Language Models in EDA ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 3

Resolution: metadata mismatch; arxiv_id, observed 2026-05-12T09:41:27.237981Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation 78dc3399-6702-4e22-ae83-99f425bcb586 · inbound

HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs cites this paper.

HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 10

Resolution: metadata mismatch; arxiv_id, observed 2026-05-12T10:36:29.744822Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation 200722e7-5f4c-450a-8e8d-b491f732e5f7 · inbound

DiagramNet: An End-to-End Recognition Framework and Dataset for Non-Standard System-Level Diagrams cites this paper.

DiagramNet: An End-to-End Recognition Framework and Dataset for Non-Standard System-Level Diagrams ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 13

Resolution: metadata mismatch; arxiv_id, observed 2026-05-11T16:51:09.203520Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation 986ac8de-1a2f-47df-961d-9d28d9678af2 · inbound

Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing cites this paper.

Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 10

Resolution: verified exact; arxiv_id, observed 2026-05-11T04:50:57.316257Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation 035b0f39-04e9-4a5d-8e1e-ded8c6be387e · inbound

Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing cites this paper.

Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 10

Resolution: verified exact; arxiv_id, observed 2026-05-25T06:55:26.237713Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation 1495336c-a5c4-43f3-bdc7-610e4a7f074e · inbound

Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing cites this paper.

Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-02T14:44:28.799059Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e7cdceb6-a98e-4126-be54-b1a098435483 · inbound

Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation cites this paper.

Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 76

Resolution: verified exact; arxiv_id, observed 2026-05-12T02:11:15.322440Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation 6623a9ef-e0bd-4ef8-86b9-4f0ba56022c6 · inbound

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation cites this paper.

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 4

Resolution: metadata mismatch; arxiv_id, observed 2026-06-29T18:53:51.281060Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation 4c7e3355-2b0a-43a0-b16f-28a86b689cf6 · inbound

StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis cites this paper.

StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 10

Resolution: verified exact; arxiv_id, observed 2026-07-02T03:56:34.641967Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation 552109fe-9bd4-4134-8389-a27fdf4347e1 · inbound

Alpha-RTL: Test-Time Training for RTL Hardware Optimization cites this paper.

Alpha-RTL: Test-Time Training for RTL Hardware Optimization ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 29

Resolution: verified exact; arxiv_id, observed 2026-07-02T07:06:44.160827Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation fcd90944-e598-4d1f-9718-de958251cfdd · inbound

Evaluating Hallucinations in Domain-Adapted Large Language Models cites this paper.

Evaluating Hallucinations in Domain-Adapted Large Language Models ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 11

Resolution: metadata mismatch; local_arxiv, observed 2026-07-05T17:21:18.073391Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation f6acce64-0037-445b-a8fb-d91692b6fa23 · inbound

Physics-informed generative AI for semiconductor manufacturing: Enforcing hard physical constraints in generative models by construction cites this paper.

Physics-informed generative AI for semiconductor manufacturing: Enforcing hard physical constraints in generative models by construction ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 30

Resolution: metadata mismatch; arxiv_id, observed 2026-07-02T23:57:28.982890Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation edc77d70-1aa2-4aa6-b30c-2f861a487335 · inbound

From AGI to ASI cites this paper.

From AGI to ASI ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 5

Resolution: metadata mismatch; arxiv_id, observed 2026-06-27T09:50:48.675786Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation 0ba6fd65-f87f-4c54-8aaf-d70e30437568 · inbound

PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design cites this paper.

PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 17

Resolution: verified exact; arxiv_id, observed 2026-07-03T19:08:49.838744Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation b0d3310d-f243-48a5-88f7-9931cd09ae5b · inbound

AgentDSE: Reasoning-Augmented Architectural Design Space Exploration cites this paper.

AgentDSE: Reasoning-Augmented Architectural Design Space Exploration ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 14

Resolution: metadata mismatch; arxiv_id, observed 2026-07-04T08:29:42.245159Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation 2e99f962-bd86-4a03-91f1-7c8396d4917d · inbound

SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows cites this paper.

SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 11

Resolution: unresolved; no resolver link, observed 2026-07-12T00:33:59.659330Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d942894e-6ea3-4f31-aa13-451918a8bafa · inbound

PCBWorld: A Benchmark Environment for Engine-Grounded PCB Design Automation cites this paper.

PCBWorld: A Benchmark Environment for Engine-Grounded PCB Design Automation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 48

Resolution: metadata mismatch; local_arxiv, observed 2026-07-08T21:15:39.006302Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.

Observation b7f8512d-87da-4ed7-b774-d2ac7fea0ba8 · inbound

PCBWorld: A Benchmark Environment for Engine-Grounded PCB Design Automation cites this paper.

PCBWorld: A Benchmark Environment for Engine-Grounded PCB Design Automation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 36

Resolution: unresolved; no resolver link, observed 2026-08-04T04:32:27.701483Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9485b45d-8e27-40a5-82ab-39aa169926c7 · inbound

LLM for EDA in Front-End Design: Challenges and Opportunities cites this paper.

LLM for EDA in Front-End Design: Challenges and Opportunities ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 2

Resolution: unresolved; no resolver link, observed 2026-07-13T01:43:21.579040Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 95bea97d-52a7-43d8-8ce7-b24173f256e2 · inbound

Quantum Circuit Vision: Cost-Aware Evaluation of Visual AI Agents for Quantum Code Generation cites this paper.

Quantum Circuit Vision: Cost-Aware Evaluation of Visual AI Agents for Quantum Code Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 25

Resolution: unresolved; no resolver link, observed 2026-07-14T00:43:41.682200Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ef7842fe-968d-4e3c-8dd3-eaaa7d713a5d · inbound

Towards Reliable AI-Assisted Analog Design: Template-Constrained LLM Agents for SAR ADC Generation cites this paper.

Towards Reliable AI-Assisted Analog Design: Template-Constrained LLM Agents for SAR ADC Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-02T05:12:20.243527Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b453e823-35d9-4085-bc38-c69922c78be9 · inbound

MAGE: Human-Like Macro Placement via Agentic Multimodal Reasoning cites this paper.

MAGE: Human-Like Macro Placement via Agentic Multimodal Reasoning ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 37

Resolution: unresolved; no resolver link, observed 2026-08-01T15:13:01.763198Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 13c02990-6943-4398-8a6e-a921cb4ec70a · inbound

RF-Agent: A Practical Framework for Building Language Agents for RFIC Design cites this paper.

RF-Agent: A Practical Framework for Building Language Agents for RFIC Design ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-01T14:27:13.511460Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d5f0c0ab-79a6-4309-a5da-e00ae4c4feb4 · inbound

Symbol and Footprint Database for Electronic Components by Agentic Recognition and Generation cites this paper.

Symbol and Footprint Database for Electronic Components by Agentic Recognition and Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-01T11:48:46.331011Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4c3f1343-d94d-4624-a3ef-712a6308ed92 · inbound

SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes cites this paper.

SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-01T06:36:59.134968Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2c39ef54-712d-47ff-bb08-26fe3cdac384 · inbound

DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models cites this paper.

DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-01T06:38:42.228129Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a95d31db-4cbd-4f22-ac8b-00f65cc41dcb · inbound

ContractHIL-HLS: Contract-Aligned Multi-Agent Workflow with Hardware-in-the-Loop Feedback for HLS Design cites this paper.

ContractHIL-HLS: Contract-Aligned Multi-Agent Workflow with Hardware-in-the-Loop Feedback for HLS Design ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-01T02:55:32.794380Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e6aa986e-093a-44d1-80d9-3bb422714b44 · inbound

ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents cites this paper.

ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 16

Resolution: unresolved; no resolver link, observed 2026-07-31T23:48:04.702842Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e3a642ab-b41d-4ecd-93d2-3edef7f48e43 · inbound

FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing? cites this paper.

FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing? ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-06T00:45:24.542140Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 62844f13-f3d4-4e08-9298-0fb537be6e66 · inbound

PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation cites this paper.

PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-04T20:50:44.998646Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f5945962-75ee-4175-963b-ddacc535ca87 · inbound

PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation cites this paper.

PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-07T00:13:00.316260Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 505af35d-6ddc-4fc1-a462-74daabbe08d1 · inbound

PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation cites this paper.

PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-07T00:59:47.940557Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0a36b807-6318-448b-912c-fed9612c360f · inbound

VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space cites this paper.

VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-15T15:01:10.196660Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d02870cf-8007-4015-9d80-0b8351ee3853 · inbound

AgenticECO: An Agentic Framework for ECO on 3D Integrated Circuits cites this paper.

AgenticECO: An Agentic Framework for ECO on 3D Integrated Circuits ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-05T13:48:51.410723Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f1d1db51-f5b5-471e-9c6f-b16c0cc75019 · inbound

NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation cites this paper.

NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-16T00:17:57.219775Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 75c0c99c-f7ac-4918-80a7-24c84152557c · inbound

SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimization cites this paper.

SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimization ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-16T00:06:27.567975Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f972c912-d010-4a23-b269-5c6b023cdc61 · inbound

Why Do Prefetchers Fail? Let Agents Answer cites this paper.

Why Do Prefetchers Fail? Let Agents Answer ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-15T18:26:17.053085Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Coverage vector

Reference resolution

Outbound references

Pith citing papers